Why am I getting “Entity port d does not match with type unsigned of component portParsing…” when I try to simulate this VHDL?
问题 The full error message is: ERROR:HDLCompiler:377 - "C:/Users/einar/Documents/Xilinx/ISE/Projects/EDA385/scale_clock_tb.vhd" Line 17: Entity port d does not match with type unsigned of component port I'm using ISE web pack and I have implemented the top module, the top module is scale_clock. Also, it simulates just fine when I do behavioral simulation. But for post-map or post-route I get the error message above. This is the code for the component: library IEEE; use IEEE.STD_LOGIC_1164.ALL;