multicore

问题 How can we devote the individual phases in UVM like run, elaboration, build etc to run on multiple cores of the system. How can this be done through coding. 回答1: As far as I know, multicore support is something you can't influence through coding. It's something your simulator either has or hasn't. Even if you could, you have the problem that your build, connect, run, etc. phase must execute in sequence. 来源： https://stackoverflow.com/questions/22296583/running-uvm-phases-on-multiple-cores

问题 Cheers, at company, we're creating a port of our games, and we need to compile PythonOgre, a wrapper of Ogre3d for Python. This is an enormous chunk of code, particularly the generated wrapper code. We have a Mac Mini with 1GB RAM. We've built i386 version. Since we have only 1GB of RAM, we've forced the build system to use only one core; second process running at the same time took a nice trip into the virtual memory. Now, we need to produce universal binaries, because publisher insists on

问题 I used -pthread for gcc compiler, but still can not find this API. any suggestion? 回答1: It's a non-standard GNU extension, as the manual and the suffix _np will tell you, so include the header like this: #define _GNU_SOURCE #include <pthread.h> 回答2: Your command must looks like this way... $ > gcc -lpthread YourProg.c if it is .cpp then >> $ > g++ -lpthread YourProg.cpp 回答3: because it is not a posix function,so maybe you can use it in somewhere,and you can not use it in some other where. So

问题 Section 2.13.2 mentions that the arbitration ID is used to determine which processor issues the no-op cycle first and I have seen this on multiple sources and the intel manual. The intel manual that references the MP initialisation sequence only addresses Pentium 4 when when there was a 'system bus' and before that there was originally an 'APIC bus'. I am under the impression that arbitration ID was only needed in those architectures where multiple cpus shared the same bus. But now, with the

问题 I have the following code which uses a single-threaded executor service, but running it uses all the 4 cores on my machine (each core around 80% usage in average). The question is why is this happening? And I am not interested here in finding Fibonacci really! public class MainSimpler { static int N=35; static AtomicInteger result = new AtomicInteger(0), pendingTasks = new AtomicInteger(1); static ExecutorService executor; public static void main(String[] args) { executor = Executors

问题 I'm designing a program and i found that assuming implicit cache coherency make the design much much easier. For example my single writer (always the same thread) multiple reader (always other threads) scenarios are not using any mutexes. It's not a problem for current Intel CPU's. But i want this program to generate income for at least the next ten years (a short time for software) so i wonder if you think this could be a problem for future cpu architectures. 回答1: I suspect that future CPU

问题 I want to make a multicore using zedboard. I have a 2 question about that. I changed a variable 'NTILES' to 2 in rocket-chip/src/main/scala/Configs.scala for implementing multicore system. If I make a multicore, how do I confirm that? I tried using fork and background execution to check the modified system, but I received error message like below picture. And pthreads couldn't be compiled. I want to know the method to confirm the multicore system. Also if you have any idea about making

问题 In a single thread program, how are changes made by thread in core 1 made visible to another core 2, so that after a context switch the thread (now running on core 2) will have updated value? Consider the following example: The value in main memory for variable x is 10. The thread runs on core 1 and changes x to 5, which is still in cache and not yet flushed to main memory as we are not using any memory barrier. A context switch occurs and the thread moves from core 1 to core 2. The thread

问题 The details of the MESI protocol for multicore processors would be really important for me, but I can't find them anywhere. Even http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf doesn't contain enough detail. For instance: assume a private L1 and shared L2 cache. If the state of a line is exclusive in L1, then is it exclusive in L2 too (or invalid, because only in one cache could be the state of a line exclusive)? And clearly, if

问题 How do I configure HAYSTACK_SOLR_URL when using multiple cores? I've set it to the address of core0, and that works, but only using one core… The docs aren't that obvious to me… it just says ... # ...or for multicore... HAYSTACK_SOLR_URL = 'http://127.0.0.1:8983/solr/mysite' What is mysite? I'm actually running apache-solar-3.3.0/example with the multicore directory copied over the example directory, and the schema and conf files/directories updated. Many thanks. 回答1: <cores adminPath="/admin