Can I force cache coherency on a multicore x86 CPU?
问题 The other week, I wrote a little thread class and a one-way message pipe to allow communication between threads (two pipes per thread, obviously, for bidirectional communication). Everything worked fine on my Athlon 64 X2, but I was wondering if I\'d run into any problems if both threads were looking at the same variable and the local cached value for this variable on each core was out of sync. I know the volatile keyword will force a variable to refresh from memory, but is there a way on