mips

问题 I'm trying to write some self modifying code in C and MIPS. Since I want to modify the code later on, I'm trying to write actual machine instructions (as opposed to inline assembly) and am trying to execute those instructions. Someone told me that it would be possible to just malloc some memory, write the instructions there, point a C function pointer to it and then jump to it. (I include the example below) I've tried this with my cross compiler (sourcery codebench toolchain) and it doesn't

问题 I am trying to figure out how to compile a simple hello world in Visual Studio, but for MIPS processor. Followed the guideline posted on MS website. Only difference is I am trying this on Visual Studio 2010: #include <iostream> int main() { std::cout << "This is a native C++ program." << std::endl; return 0; } Tried compiling with the /QMR4100 options: c:\Users\ukhan\Documents\Auto_Security\Test_Code>cl /QMR4100 /EHsc forloop.cpp Microsoft (R) C/C++ Optimizing Compiler Version 16.00.30319.01

问题 I am currently working on a program that counts the number of 1's in an integer's binary representation, where the integer is entered by the user. I need to do it so that the program runs from top down, so that means no loops or flow of instruction of any kind. However, I am very new to Mips and assembly language, and am currently struggling with how to do this. I think that you can use the srlv and/or sllv instructions for this with some multiplication, but I have no clue even where to start

问题 Currently, I'm learning GNU as, and find a lot useful information in "info as". I found ".set noat" is used in MIPS specified code, but when searching for this directive in "info as", I found its explanation in node "alpha directive", but not in "MIPS Dependent Features". Why? did I miss something in the manual? TIA 回答1: The .set at/noat is a valid construction for MIPS architecture and works the similar way as on Alpha by disabling/enabling warning when $at register is used by user. As

问题 What do we mean by the pointer based array access in MIPS? 回答1: There is an additional possible meaning or implication to "pointer based array access": You may have a pointer to an array, rather than an array at a fixed address. Actually, in C/C++, a "pointer to an array" is really usually just a pointer to the first element of the array. Basically, you have an array that is a parameter to a function, or a pointer to an array that is a member of a struct or class: void Foo(char a[]); /*or*/

问题 add rd, rs, rt addu rd, rs, rt sub rd, rs, rt subu rd, rs, rt In MIPS, what's the difference between signed addition, unsigned addition, signed subtraction and unsigned subtraction? If their results are the same, what's the point to classified as using signed and unsigned methods? 回答1: The u simply means that they don't trap on overflow. Quoting from "MIPS32 Architecture For Programmers Volume II": The term "unsigned" in the instruction name is a misnomer; this operation is 32-bit modulo

问题 In MIPS, the la instruction translates into lui and ori . However, MARS Simulator does not seem to do that at all. When I dump the following machine code: .text la $a0, array la $a1, array_size lw $a1, 0($a1) .data array: .word 0:10 array_size: .word 10 message: .asciiz "The sum of numbers in array is: " I get: 00100000000001000010000000000000 00100000000001010010000000101000 10001100101001010000000000000000 Which is obviously. It is dumping la as one instruction. What does MARS do? How can I

问题 I'm working on translating the below C++ code to MIPS (this is just a small portion of the program that I'm stuck on), and I understand the gist of how to set $t registers to take the array values given, but I'm completely stuck on pos[count] = i; I've tried sw , lw , but everytime I try these, I get address out of range exceptions/etc. Can someone explain to me what's going wrong here? When the loop gets to pos[count] = i , I need to change pos[count] from 0xffffffff to (i) for each loop

问题 For example on add we have addi for adding a register and an immediate,why on this case we cant have bnei or beqi... Im supposed to answer on that,but im not sure...any help? 回答1: The reason is the instruction encoding: Both ADDI and BNE/BEQ are I-Type instructions. But whereas the immediate field in the ADDI instruction is used for storing the immediate operand for the addition, it's used for storing the branch offset in the case of BEQ/BNE . There may be MIPS assemblers which allow you to

问题 For example on add we have addi for adding a register and an immediate,why on this case we cant have bnei or beqi... Im supposed to answer on that,but im not sure...any help? 回答1: The reason is the instruction encoding: Both ADDI and BNE/BEQ are I-Type instructions. But whereas the immediate field in the ADDI instruction is used for storing the immediate operand for the addition, it's used for storing the branch offset in the case of BEQ/BNE . There may be MIPS assemblers which allow you to