microprocessors

问题 What does the below comment mean in Intel Processor data sheet? How can I check that in my driver's code in Linux? If CPUID.06H:EAX.[7] = 1 I come across this type of statements in the SW developer's manual for Intel Processors in the comments column in register description table.. Ref: https://software.intel.com/sites/default/files/managed/22/0d/335592-sdm-vol-4.pdf Please help me to understand the processor descriptions. Thanks. 回答1: CPUID.06H:EAX.[7] enables the discovery of the HWP

问题 MTS-88.C and I/O BOARD -08 has 8 (Eight) 7-segment displays and 20 key-pads on board. The displays are numbered from 7-SEG.1 to 7-SEG.8 and are connected to Port B’s PB7 to PB0 lines respectively. To display a character on a 7-segment display a byte has to be written to port B. The MSB 4 bits are the address of the 7-segment display and LSB 4 bits are the data. So if we write 58 H to port B then the 6th 7-segment display will show data 8. 20 key-pads are numbered from P01 to P20 and are

问题 What'll be the behaviour of the 8086 Microprocessor when the stack is full and even then I push something into it? 回答1: On the 8086, a PUSH instruction or implicit stack push will decrement the SP register by two and store the appropriate quantity at SS:SP (i.e. 16*SS+SP). If the SP register was $0000, the data will go to SS:$FFFE. If the SP register was $0001, the MSB of the data will go to SS:$0000 and the LSB will go to SS:$FFFF. The processor will not take any special notice of the stack

问题 I want to know if there a routine or an instruction to generate a random number using assembly on 8086. any help will be appreciated. 回答1: The most common way is to use the timestamp. In 32 bit mode it can be done by rdtsc instruction, in 16 bit mode: by using function 0 of BIOS interrupt 1A. Because it's a timestamp, avoid using it frequently (because of lack of proper dispersion), and use it as seed for an pseudo-random number generator. When you need just one random value, you can use the

问题 In the 8086 architecture, the memory space is 1 MiB in size and divided into logical segments of up to 64 KiB each. i.e. it has 20 address lines thus the following method is used: That the data segment register is shifted left 4 bits then added to the offset register My question is: How we do the shift operation although all the registers are only 16 bits 回答1: Address translation is done internally by a special unit without using the registers available to user code to store intermediate

问题 As mentioned in the question , I was wondering whether it is possible for the controller to detect two button press simultaneously. I am new to controller programming and started with the basics - blinking LED, then moved to buttons and now trying to play around button presses. I wanted to set some flag when both buttons are pressed together . But as of I know, Only one ISR will be called in this case, thus detecting a single press. How can we achieve this... (In some electronic devices, it

问题 I am unable to understand how does the direction flag work in x86 . The text in my lectures say that it increments or decrements the source or destination register but that does not make sense with its name. Can someone explain what it does? 回答1: This flag is used in string operations, and specifies if strings begin at a low address and proceed to higher addresses or vice versa. For string instructions, ECX has the number of iterations, DS:ESI has the source address and ES:EDI has the

问题 I want to measure how long does a single function take on STM32. The only thing I could find is SysTick_Handler . However, that is an periodic interrupt, but what I need is get time interval like: long t1 = mcu_clock(); sleep(20); long t2 = mcu_clock(); long diff = (t2 - t1); I've tried C clock() , but it didn't work and always return -1 . How can I make it? 回答1: First, enable the cycle counter once at startup: CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; DWT->CYCCNT = 0; DWT->CTRL |= DWT

问题 I think,since memory of intel microprocessors is byte organized and size of instruction queue is 4 bytes,the answer would be 4 instructions? 回答1: The 8086 and 8088 chips have prefetch queues. These stored a number of bytes pre-fetched from the memory "ahead" of the instruction pointer (and code segment). This allows the processor to do something "useful" in what otherwise would have been an idle bus cycles. The 8088 prefetch queue was four bytes deep. The 8086 queue was six bytes deep. Again,

问题 I am unable to understand the different starting addresses of Physical Address generated by CS:IP in 8085-86. Is this because of Stack? I think the concept of Stack was present before 8085. Please help out. Thanks. 回答1: There are 3 reasons I can think of that a particular value could be used for the powerup IP: convention - other processors in the same family/brand use the same location, and they want to give their customers a sense of familiarity compatibility certain areas are restricted or