memory-segmentation

问题 The physical address of the memory cell is given in the form 1A32H. What is the address of the beginning of the memory segment. Or more exactly, the seg:off address I should use to access it. Can someone explain me step by step how to solve this problem? 回答1: In x86 real-mode, the physical address is calculated as: 16 * segment + offset So the physical address 1A32H can be accessed in different ways: Segment = 1A3H, Offset = 2 or Segment = 1A2H, Offset = 12H or Segment = 1A1H, Offset = 22H or

问题 While reading The Art of Assembly the other day, I came to the section here on memory layout. It started discussing segmented memory, and I didn't think it made a lot of sense. Splitting memory into segments makes perfect sense as a way for organization, but using the function segment + offset , what do you do when the function repeats its outputs? e.g. 1038 + 57 , 57 + 1038 , and 1095 + 0 all come out to the linear address 1095. Isn't that a bad thing? Wouldn't you accidentally address the

问题 While reading The Art of Assembly the other day, I came to the section here on memory layout. It started discussing segmented memory, and I didn't think it made a lot of sense. Splitting memory into segments makes perfect sense as a way for organization, but using the function segment + offset , what do you do when the function repeats its outputs? e.g. 1038 + 57 , 57 + 1038 , and 1095 + 0 all come out to the linear address 1095. Isn't that a bad thing? Wouldn't you accidentally address the

问题 Duntemann says 8086 could address 16 times as much memory as 8080 and has gone on to elaborate upon this as 16 * 64K = 1MB . So I am assuming 16 bits at a time (16-bit processor) * 64K because 16 address lines (2^16). But, by that logic for calculation shouldn't 8080 (8-bit processor) also having 16 address lines have been able to address 8 * 64K = 0.5MB? shouldn't the 8086 then be able to address twice as much as 8080? 回答1: 16x is the difference between 2^20 and 2^16 . The 8080 has 16 bits

问题 I am writing my own OS for 64bit processors and I am stuck with the problem of general protection. My OS will not rely on page fault to implement user space protection mechanism, so I found there is a way to do it with segment limit checking: This presentation from VMWare http://download3.vmware.com/vmworld/2005/pac346.pdf on page 20 says: Initial AMD64 architecture did not include segmentation in 64-bit mode Segmentation also missing from EMT64T How do we protect the VMM ? 64-bit guest

问题 IAPX88 can deal with 1 mega byte memory(20 bit addressing), now my question is how we make a 20 bit address by using two 16 bit registers.please give an example. 回答1: IAPX88 physical addresses are computed by taking the segment register, shifting it to the left 4 bits, and adding the offset register. For example, the physical address in memory that code executes is (CS<<4)+IP where CS is the Code Segment and IP is the Instruction Pointer. You can get details on the Intel 8086 wikipedia page.

问题 When I run the emu8086, this result(ans) return to me 0 ..Why ? data segment ans dw ? ends stack segment dw 128 dup(0) ends code segment start: mov ax,@data mov dx,ax mov ax,2 mov bl,2 mul bl mov ans,ax mov ax, 4c00h int 21h ends end start 回答1: mov ax,@data mov dx,ax This part of the code must setup the DS segment register. You made a typo and wrote DX instead! mov ax, @data mov ds, ax Because of this error, the result of your AL * BL multiplication (4) was still written in memory by mov ans

问题 According to AMD manual segmentation can not be disabled. My question is why, why it's impossible? Another question, it says that 64-bit disables it, what does that mean? Is segmentation completly disabled on 64-bit mode? AMD Manual: https://s7.postimg.cc/hk15o6swr/Capture.png 回答1: Introduction In 64-bit mode, whenever a non-null segment selector is loaded into any of the segment registers, the processor automatically loads the corresponding segment descriptor in the hidden part of the

问题 So, I know that Linux uses four default segments for an x86 processor (kernel code, kernel data, user code, user data), but they all have the same base and limit (0x00000000 and 0xfffff), meaning each segment maps to the same set of linear addresses. Given this, why even have user/kernel segments? I understand why there should be separate segments for code and data (just due to how the x86 processor deals with the cs and ds registers), but why not have a single code segment and a single data

问题 I have one doubt regarding the size of segments in real mode as they can't be more than 64K but can be less than that. My question is how these segment size and base address is initialized ? Like there are GDT's and LDT's in protected mode.Real mode segments can also overlapped,disjoint or adjacent.Like BIOS has some reserved area for specific things like boot code,video buffer etc does assembly programs need to do something like that ? 回答1: In real mode segmented addresses are hardwired into