memory-fences

I have heard that when dealing with mutexes, the necessary memory barriers are handled by the pthread API itself. I would like to have more details on this matter. Are these claimings true, at least on the most common architectures around? Does the compiler recognize this implicit barrier, and avoids reordering of operations/read from local registers when generating the code? When is the memory barrier applied: after successfully acquiring a mutex AND after releasing it? The POSIX specification lists the functions that must "synchronize memory with respect to other threads" , which includes

I'm writing some threaded C++11 code, and I'm not totally sure on when I need to use a memory fence or something. So here is basically what I'm doing: class Worker { std::string arg1; int arg2; int arg3; std::thread thread; public: Worker( std::string arg1, int arg2, int arg3 ) { this->arg1 = arg1; this->arg2 = arg2; this->arg3 = arg3; } void DoWork() { this->thread = std::thread( &Worker::Work, this ); } private: Work() { // Do stuff with args } } int main() { Worker worker( "some data", 1, 2 ); worker.DoWork(); // Wait for it to finish return 0; } I was wondering, what steps do I need to

I am trying to understand what is a memory barrier exactly. Based on what I know so far, a memory barrier (for example: mfence ) is used to prevent the re-ordering of instructions from before to after and from after to before the memory barrier. This is an example of a memory barrier in use: instruction 1 instruction 2 instruction 3 mfence instruction 4 instruction 5 instruction 6 Now my question is: Is the mfence instruction just a marker telling the CPU in what order to execute the instructions? Or is it an instruction that the CPU actually executes like it executes other instructions (for

According to the Intel 64 and IA-32 Architectures Software Developer's Manual the LOCK Signal Prefix "ensures that the processor has exclusive use of any shared memory while the signal is asserted". That can be a in the form of a bus or cache lock. But - and that's the reason I'm asking this question - it isn't clear to me, if this Prefix also provides any memory-barrier. I'm developing with NASM in a multi-processor environment and need to implement atomic operations with optional acquire and/or release semantics. So, do I need to use the MFENCE, SFENCE and LFENCE instructions or would this

I'm reading Memory Barriers by Paul E. McKenney http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf everything is explained in great details and when I see that everything is clear I encounter one sentence, which stultifies everything and make me think that I understood nothing. Let me show the example void foo(void) { a = 1; #1 b = 1; #2 } void bar(void) { while (b == 0) continue; #3 assert(a == 1); #4 } let's say this two functions are running on a different processors. Now what could possibly happen is store to a #1 could be seen after store to b #2 by the second