memory-barriers

问题 I am reading these days about memory fences and barriers as a way to synchronize multithreaded code and avoid code reordering. I usually develop in C++ under Linux OS and I use boost libs massively but I am not able to find any class related to it. Do you know if memory barrier of fences are present in boost or if there is a way to achieve the same concept? If not what good library can I have a look to? 回答1: There are no low-level memory barriers in boost yet, but there is a proposed boost

问题 I see C++11 mutexes lock is not void lock() volatile . How does the compiler know which functions are memory barriers and which are not? Are all functions barriers even if they are not volatile? What are some less known memory barriers and memory barriers everyone should know? 回答1: The runtime library has to implement a mutex in a way so that the compiler knows! The language standard doesn't say anything about how to do this. Likely, it involves a call to some operating system service that

问题 I am unsure about how the memory ordering guarantees of atomic variables in c++11 affect operations to other memory. Let's say I have one thread which periodically calls the write function to update a value, and another thread which calls read to get the current value. Is it guaranteed that the effects of d = value; will not be seen before effects of a = version; , and will be seen before the effects of b = version; ? atomic<int> a {0}; atomic<int> b {0}; double d; void write(int version,

问题 Below is an example given in Concurrency in Action , and the author says the assert may fire, but I don't understand why. #include <atomic> #include <thread> #include <assert.h> std::atomic<bool> x,y; std::atomic<int> z; void write_x_then_y() { x.store(true,std::memory_order_relaxed); y.store(true,std::memory_order_relaxed); } void read_y_then_x() { while(!y.load(std::memory_order_relaxed)); if(x.load(std::memory_order_relaxed)) ++z; } int main() { x=false; y=false; z=0; std::thread a(write_x

问题 I am experimenting with non-temporal instructions, and am already familiar with how fences with ordinary load/stores operate. Intel defines an intrinsic, _mm_sfence, in relation with non-temporal operations, which the manual defines as: Guarantees that every preceding store is globally visible before any subsequent store. I have some questions about this operation. Is this just inserting a SFENCE instruction? If not, what does this translate to? If this is not just a SFENCE, does a SFENCE

问题 Based on a previous question, I was wondering if the following code would work to compute lower and upper bounds to the average value of a property being measured using atomics: std::atomic< unsigned int > m_accLower; std::atomic< unsigned int > m_countLower; std::atomic< unsigned int > m_accUpper; std::atomic< unsigned int > m_countUpper; // ... void Class::UpdateLower( unsigned int delta ) { m_countLower.fetch_add( 1 , std::memory_order_relaxed ); m_accLower.fetch_add( delta , std::memory

问题 Say there are two functions to update and return the average of some property being measured: void Class::Update( int delta ) { m_accumulatedValue += delta; ++ m_count; } double Class::GetAverage( ) { return m_accumulatedValue/(double)m_count; } Now, suppose they need to be changed to run in a multithreaded environment with a thread pool in which any thread can be requested to execute one of them - that is, the thread executing each one of them can be a different one each time: std::atomic<

问题 The Intel Architectures Software Developer's Manual, Aug. 2012, vol. 3A, sect. 8.2.2: Any two stores are seen in a consistent order by processors other than those performing the stores. But can this be so? The reason I ask is this: Consider a dual-core Intel i7 processor with HyperThreading. According to the Manual's vol. 1, Fig. 2-8, the i7's logical processors 0 and 1 share an L1/L2 cache, but its logical processors 2 and 3 share a different L1/L2 cache -- whereas all the logical processors

问题 (I know they don't but I'm looking for the underlying reason this actually works without using volatile since there should be nothing preventing the compiler from storing a variable in a register without volatile... or is there...) This question stems from the discord of thought that without volatile the compiler (can optimize in theory any variable in various ways including storing it in a CPU register.) While the docs say that is not needed when using synchronization like lock around

问题 I have a simple linked list. There is no danger of the ABA problem, I'm happy with Blocking category and I don't care if my list is FIFO, LIFO or randomized. At long as the inserting succeeds without making others fails. The code for that looks something like this: class Class { std::atomic<Node*> m_list; ... }; void Class::add(Node* node) { node->next = m_list.load(std::memory_order_acquire); while (!m_list.compare_exchange_weak(node->next, node, std::memory_order_acq_rel, std::memory_order