memory-barriers

问题 Suppose I have a thread A that writes to an atomic_int x = 0; , using x.store(1, std::memory_order_relaxed); . Without any other synchronization methods, how long would it take before other threads can see this, using x.load(std::memory_order_relaxed); ? Is it possible that the value written to x stays entirely thread-local given the current definition of the C/C++ memory model that the standard gives? The practical case that I have at hand is where a thread B reads an atomic_bool frequently

问题 I've looked through the TI C/C++ compiler v6.1 user's guide (spru514e) but didn't find anything. The asm statement doesn't seem to provide anything in this regard, the manual even warns against changing values of variables (p132). The GNU extension for declaring effects on variables is not implemented (p115). I also didn't find any intrinsic for memory barriers (like __memory_changed() in Keil's armcc). Searching the web or the TI forums also turned up nothing. Any other hints how to proceed?

问题 Suppose that I want to use a boolean status flag for cooperative cancellation between threads. (I realize that one should preferably use CancellationTokenSource instead; that is not the point of this question.) private volatile bool _stopping; public void Start() { var thread = new Thread(() => { while (!_stopping) { // Do computation lasting around 10 seconds. } }); thread.Start(); } public void Stop() { _stopping = true; } Question : If I call Start() at 0s and Stop() at 3s on another

问题 The C++0x draft has a notion of fences which seems very distinct from a CPU/chip level notion of fences, or say what the linux kernel guys expect of fences. The question is whether the draft really implies an extremely restricted model, or the wording is just poor and it actually implies true fences. For example, under 29.8 Fences it states things like: A release fence A synchronizes with an acquire fence B if there exist atomic operations X and Y, both operating on some atomic object M, such

问题 The C++0x draft has a notion of fences which seems very distinct from a CPU/chip level notion of fences, or say what the linux kernel guys expect of fences. The question is whether the draft really implies an extremely restricted model, or the wording is just poor and it actually implies true fences. For example, under 29.8 Fences it states things like: A release fence A synchronizes with an acquire fence B if there exist atomic operations X and Y, both operating on some atomic object M, such

问题 I know that modern CPUs can execute out of order, However they always retire the results in-order, as described by wikipedia. "Out of Oder processors fill these "slots" in time with other instructions that are ready, then re-order the results at the end to make it appear that the instructions were processed as normal. " Now memory fences are said to be required when using multicore platforms, because owing to Out of Order execution, wrong value of x can be printed here. Processor #1: while f

问题 As far as I have understood, mfence is a hardware memory barrier while asm volatile ("" : : : "memory") is a compiler barrier. But,can asm volatile ("" : : : "memory") be used in place of mfence. The reason I have got confused is this link 回答1: Well, a memory barrier is only needed on architectures that have weak memory ordering. x86 and x64 don't have weak memory ordering. on x86/x64 all stores have a release fence and all loads have an acquire fence. so, you should only really need asm

问题 From the speech Herb Sutter in the figure of the slides on page 2: https://skydrive.live.com/view.aspx?resid=4E86B0CF20EF15AD!24884&app=WordPdf&wdo=2&authkey=!AMtj_EflYn2507c Here are shown separate cache- L1S and Store Buffer ( SB ). 1. In processors Intel x86 cache-L1 and Store Buffer - is the same thing? And next slide: As we see from the next slide in the x86 is only possible following reordering. was: MOV eax, [memory1] / / read MOV [memory2], edx / / write ... / / MOV, MFENCE, ADD ...

问题 I'm checking how the compiler emits instructions for multi-core memory barriers on x86_64. The below code is the one I'm testing using gcc_x86_64_8.3 . std::atomic<bool> flag {false}; int any_value {0}; void set() { any_value = 10; flag.store(true, std::memory_order_release); } void get() { while (!flag.load(std::memory_order_acquire)); assert(any_value == 10); } int main() { std::thread a {set}; get(); a.join(); } When I use std::memory_order_seq_cst , I can see the MFENCE instruction is

问题 Say, I have two threads A and B writing to a global Boolean variables fA and fB respectively which are initially set to false and are protected by std::mutex objects mA and mB respectively: // Thread A mA.lock(); assert( fA == false ); fA = true; mA.unlock(); // Thread B mB.lock() assert( fB == false ); fB = true; mB.unlock() Is it possible to observe the modifications on fA and fB in different orders in different threads C and D ? In other words, can the following program #include <atomic>