memory-barriers

问题 As we know from a previous answer to Does it make any sense instruction LFENCE in processors x86/x86_64? that we can not use SFENCE instead of MFENCE for Sequential Consistency. An answer there suggests that MFENCE = SFENCE + LFENCE , i.e. that LFENCE does something without which we can not provide Sequential Consistency. LFENCE makes impossible to reordering: SFENCE LFENCE MOV reg, [addr] -- To --> MOV reg, [addr] SFENCE LFENCE For example reordering of MOV [addr], reg LFENCE --> LFENCE MOV

问题 The Intel Memory Model guarantees: Stores will not be re-ordered with other Stores Loads will not be re-ordered with other Loads http://bartoszmilewski.com/2008/11/05/who-ordered-memory-fences-on-an-x86/ I have seen claims that SFENCE is redundant on x86-64 due to the Intel memory model, but never LFENCE. Do the above memory model rules make either instructions redundant? 回答1: Right, LFENCE and SFENCE are not useful in normal code because x86's acquire / release semantics for regular stores

问题 I have found out that an x86 CPU have the following memory barriers instructions: mfence , lfence , and sfence . Does an x86 CPU only have these three memory barriers instructions, or are there more? 回答1: sfence (SSE1) and mfence / lfence (SSE2) are the only instructions that are named for their memory fence/barrier functionality . Unless you're using NT loads or stores and/or WC memory, only mfence is needed for memory ordering. (Note that lfence on Intel CPUs is also a barrier for out-of

问题 In recent Intel ISA documents the lfence instruction has been defined as serializing the instruction stream (preventing out-of-order execution across it). In particular, the description of the instruction includes this line: Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruction begins execution until LFENCE completes. Note that this applies to all instructions, not just memory load instructions, making lfence more than just a

问题 What I\'m wondering is if lock xchg will have similar behavior to mfence from the perspective of one thread accessing a memory location that is being mutated (lets just say at random) by other threads. Does it guarantee I get the most up to date value? Of memory read/write instructions that follow after? The reason for my confusion is: 8.2.2 “Reads or writes cannot be reordered with I/O instructions, locked instructions, or serializing instructions.” -Intel 64 Developers Manual Vol. 3 Does

问题 C# 4 in a Nutshell (highly recommended btw) uses the following code to demonstrate the concept of MemoryBarrier (assuming A and B were run on different threads): class Foo{ int _answer; bool complete; void A(){ _answer = 123; Thread.MemoryBarrier(); // Barrier 1 _complete = true; Thread.MemoryBarrier(); // Barrier 2 } void B(){ Thread.MemoryBarrier(); // Barrier 3; if(_complete){ Thread.MemoryBarrier(); // Barrier 4; Console.WriteLine(_answer); } } } they mention that Barriers 1 & 4 prevent

问题 8.1.2 Bus Locking Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically during certain critical memory operations to lock the system bus or equivalent link. While this output signal is asserted, requests from other processors or bus agents for control of the bus are blocked. Software can specify other occasions when the LOCK semantics are to be followed by prepending the LOCK prefix to an instruction. It comes from Intel Manual, Volume 3 It sounds like the atomic

问题 Some languages provide a volatile modifier that is described as performing a \"read memory barrier\" prior to reading the memory that backs a variable. A read memory barrier is commonly described as a way to ensure that the CPU has performed the reads requested before the barrier before it performs a read requested after the barrier. However, using this definition, it would seem that a stale value could still be read. In other words, performing reads in a certain order does not seem to mean

问题 In \"C# 4 in a Nutshell\", the author shows that this class can write 0 sometimes without MemoryBarrier , though I can\'t reproduce in my Core2Duo: public class Foo { int _answer; bool _complete; public void A() { _answer = 123; //Thread.MemoryBarrier(); // Barrier 1 _complete = true; //Thread.MemoryBarrier(); // Barrier 2 } public void B() { //Thread.MemoryBarrier(); // Barrier 3 if (_complete) { //Thread.MemoryBarrier(); // Barrier 4 Console.WriteLine(_answer); } } } private static void

问题 Reading Joseph Albahari\'s threading tutorial, the following are mentioned as generators of memory barriers: C#\'s lock statement ( Monitor.Enter / Monitor.Exit ) All methods on the Interlocked class Asynchronous callbacks that use the thread pool — these include asynchronous delegates, APM callbacks, and Task continuations Setting and waiting on a signaling construct Anything that relies on signaling, such as starting or waiting on a Task In addition, Hans Passant and Brian Gideon added the