memory-barriers

What I'm wondering is if lock xchg will have similar behavior to mfence from the perspective of one thread accessing a memory location that is being mutated (lets just say at random) by other threads. Does it guarantee I get the most up to date value? Of memory read/write instructions that follow after? The reason for my confusion is: 8.2.2 “Reads or writes cannot be reordered with I/O instructions, locked instructions, or serializing instructions.” -Intel 64 Developers Manual Vol. 3 Does this apply across threads? mfence states: Performs a serializing operation on all load-from-memory and

As we know from a previous answer to Does it make any sense instruction LFENCE in processors x86/x86_64? that we can not use SFENCE instead of MFENCE for Sequential Consistency. An answer there suggests that MFENCE = SFENCE + LFENCE , i.e. that LFENCE does something without which we can not provide Sequential Consistency. LFENCE makes impossible to reordering: SFENCE LFENCE MOV reg, [addr] -- To --> MOV reg, [addr] SFENCE LFENCE For example reordering of MOV [addr], reg LFENCE --> LFENCE MOV [addr], reg provided by mechanism - Store Buffer , which reorders Store - Loads for performance

8.1.2 Bus Locking Intel 64 and IA-32 processors provide a LOCK# signal that is asserted automatically during certain critical memory operations to lock the system bus or equivalent link. While this output signal is asserted, requests from other processors or bus agents for control of the bus are blocked. Software can specify other occasions when the LOCK semantics are to be followed by prepending the LOCK prefix to an instruction. It comes from Intel Manual, Volume 3 It sounds like the atomic operations on memory will be executed directly on memory (RAM). I am confused because I see "nothing

In recent Intel ISA documents the lfence instruction has been defined as serializing the instruction stream (preventing out-of-order execution across it). In particular, the description of the instruction includes this line: Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruction begins execution until LFENCE completes. Note that this applies to all instructions, not just memory load instructions, making lfence more than just a memory ordering fence. Although this now appears in the ISA documentation, it isn't clear if it is