intel

问题 How do I test if a __m128i variable has any nonzero value on SSE-2-and-earlier processors? 回答1: In SSE2 you can do: __m128i zero = _mm_setzero_si128(); if(_mm_movemask_epi8(_mm_cmpeq_epi32(x,zero)) == 0xFFFF) { //the code... } this will test four int's vs zero then return a mask for each byte, so your bit-offsets of each corresponding int would be at 0, 4, 8 & 12, but the above test will catch if any bit is set, then if you preserve the mask you can work with the finer grained parts directly

问题 Closed . This question is opinion-based. It is not currently accepting answers. Want to improve this question? Update the question so it can be answered with facts and citations by editing this post. Closed 2 years ago . When using assembly instructions on x86 or amd64, programmer can use "Intel" (i.e. nasm compiler) or "AT&T" (i.e. gas compiler) assembly syntax. "Intel" syntax is more popular on Windows, but "AT&T" is more popular on UNIX(-like) systems. But both Intel and AMD manuals, so

问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 2 years ago . Ideally there would be a version of Intel's Software Developer's Manuals written in AT&T syntax, but I would be happy to find anything that is close enough. 回答1: Sun's manual uses gas syntax, with a correspondence table for the Intel/AMD-sanctioned opcode names (PDF). 来源： https://stackoverflow.com/questions

问题 can anyone explain what is load buffer and how it's different from invalidation queues. and also difference between store buffers and write combining buffers? The paper by Paul E Mckenny http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf explains very nicely about the store buffers and invalidation queues but unfortunately doesn't talk about write combining buffers 回答1: An invalidate queue is more like a store buffer, but it's part of the memory system, not the CPU.

问题 can anyone explain what is load buffer and how it's different from invalidation queues. and also difference between store buffers and write combining buffers? The paper by Paul E Mckenny http://www.rdrop.com/users/paulmck/scalability/paper/whymb.2010.07.23a.pdf explains very nicely about the store buffers and invalidation queues but unfortunately doesn't talk about write combining buffers 回答1: An invalidate queue is more like a store buffer, but it's part of the memory system, not the CPU.

问题 Lately Google and Intel have published a new way to run the emulator, which should work much better than the previous version (which has emulated ARM CPU). Here are some links about it: this and this. However, after installing the new components and creating a new emulator configuration as instructed, I get an error and I also can't see any improvements. I've tried both API 10 and API 15, and with GPU enabled and disabled. None of those configurations helped. I've also tried it on two

问题 I've been trying to figure out a performance problem in an application and have finally narrowed it down to a really weird problem. The following piece of code runs 6 times slower on a Skylake CPU (i5-6500) if the VZEROUPPER instruction is commented out. I've tested Sandy Bridge and Ivy Bridge CPUs and both versions run at the same speed, with or without VZEROUPPER . Now I have a fairly good idea of what VZEROUPPER does and I think it should not matter at all to this code when there are no

问题 Just as an example, I want to know exactly which of the x86 processor families support the fisttp instruction. I'm pretty certain that it's supported on the Pentium 4 and beyond, but I'd like to have some official verification of that. And more importantly, I'd like to know if it is supported any further back: is it available on the Pentium III? I tried all the obvious Google search terms, but there's hardly anything at all available online about this particular instruction. And even if there

问题 I am trying to develop my own basic kernel for educational purpose. I was reading the Intel 80386 and reading about the the interrupt 0 :- Divide by zero exception. In there, it was written :- Saved Instruction Pointer Saved contents of CS and EIP registers point to the instruction that generated the exception. My question is where are these registers saved. How, can I access these registers ? 回答1: An Interrupt pushes the current contents of the EFLAGS, CS, and EIP registers (in that order)

问题 I am trying to debug a segmentation fault in my assembly code. Here is the GDB output Program received signal SIGSEGV, Segmentation fault. 0x0000000000424c50 in restore_context() (gdb) disassemble restore_context Dump of assembler code for function restore_context: 0x0000000000424c44 <+0>: mov 0x8(%rsp),%rax 0x0000000000424c49 <+5>: mov 0x38(%rax),%rsp 0x0000000000424c4d <+9>: mov (%rax),%rdx =>0x0000000000424c50 <+12>: mov %rdx,(%rsp) 0x0000000000424c54 <+16>: mov 0x18(%rax),%rbx