instructions

问题 I like examples, so I wrote a bit of self-modifying code in c... #include <stdio.h> #include <sys/mman.h> // linux int main(void) { unsigned char *c = mmap(NULL, 7, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE| MAP_ANONYMOUS, -1, 0); // get executable memory c[0] = 0b11000111; // mov (x86_64), immediate mode, full-sized (32 bits) c[1] = 0b11000000; // to register rax (000) which holds the return value // according to linux x86_64 calling convention c[6] = 0b11000011; // return for (c[2] = 0; c

问题 I just started learning about micro controllers and I was not able to understand how we could introduce delays in the code without using timers. My board has a clock of 16MHZ. Let's say I want to introduce 5ms delay before I check if a button is pressed. How would I identify how many instructions I need to execute to get 5 ms delay and how would I program it? Is there a standardized way of doing this? It looks like a very standard thing but I am not able to understand how it is done. I am

问题 I'm trying to learn assembly (so bear with me) and I'm getting a compile error on this line: mov byte [t_last], [t_cur] The error is error: invalid combination of opcode and operands I suspect that the cause of this error is simply that its not possible for a mov instruction to move between two memory addresses, but half an hour of googling and I haven't been able to confirm this - is this the case? Also, assuming I'm right that means I need to use a register as an intermediate point for

问题 is there a way to read given amount of instructions from a binary executable file on x86 architecture programmatically? If I had a binary of a simple C program hello.c : #include <stdio.h> int main(){ printf("Hello world\n"); return 0; } Where after compilation using gcc , the disassembled function main looks like this: 000000000000063a <main>: 63a: 55 push %rbp 63b: 48 89 e5 mov %rsp,%rbp 63e: 48 8d 3d 9f 00 00 00 lea 0x9f(%rip),%rdi # 6e4 <_IO_stdin_used+0x4> 645: e8 c6 fe ff ff callq 510

问题 I'm doing something about function safety. I need verify some X86 CPU instructions, such as LFENCE, SFENCE and MFENCE. Now I can experience MFENCE according to Intel SDM chapter 8.2.3.4 "loads may be reordered with earlier store to different location". "xor %0, %0\n\t " "movl $1, %1\n\t " "mfence\n\t " "movl %2, %0\n\t " : "=r"(r1), "=m" (X) : "m"(Y) : "memory"); "xor %0, %0\n\t " "movl $1, %1\n\t " "mfence\n\t " "movl %2, %0\n\t " : "=r"(r2), "=m" (Y) : "m"(X) : "memory"); Above code only

问题 I'm not sure what is the range bound for the immediate in lui instruction. When I assemble: lui $t0,32768 It successfully went without errors. However, lui $t0,-32768 notified that -32768 out of range. 回答1: In MIPS the immediate in I-type instructions is always 16-bit long. That means the range will be [0, 65535] if the assembler treats it as unsigned, and [-32768, 32767] for the signed case However what you can use in the assembly depends on the assembler For example some assemblers like

问题 Recent Intel and AMD CPUs support specific AES instructions that increase the performance of encryption and decryption. Is it possible to to detect when these instructions are called? For example by writing a kernel module that monitors the instructions that are sent to the CPU? Or is the kernel still to high-level? 回答1: My understanding is that instructions like AESENC require no special privileges, so you won't be able to trap them with one of the usual fault handlers even in the kernel.

问题 This statement: reg [7:0] register_file [3:0] = 0; Produces this error: Error (10673): SystemVerilog error at simpleprocessor.v(27): assignments to unpacked arrays must be aggregate expressions First of all I am using Verilog, not SystemVerilog, so why is it giving me a SystemVerilog error? Second of all, what is the cause of this error, and how can I fix it? I am using it in my desgin of a very rudementary processor to represent the internal working registers as a multidemmnsional array of

问题 I think,since memory of intel microprocessors is byte organized and size of instruction queue is 4 bytes,the answer would be 4 instructions? 回答1: The 8086 and 8088 chips have prefetch queues. These stored a number of bytes pre-fetched from the memory "ahead" of the instruction pointer (and code segment). This allows the processor to do something "useful" in what otherwise would have been an idle bus cycles. The 8088 prefetch queue was four bytes deep. The 8086 queue was six bytes deep. Again,

问题 I have an assignment that I'm supposed to implement the MIPS processor in C++ and one of the MIPS instructions is "AND" and "OR" the MIPS instruction is represented as and $s1,$s2,$s3 which means that $s1=$s2(and)$s3 the $s2 and $s3 registers are represented into bits ,,, how can I perform the "AND" and "OR" operations using C++? 回答1: There are both binary and logical and and or operators in C++. int a, b = 1; int x = a | b; // binary OR int x = a & b; // binary AND bool x = a || b; //