fsm

What is the Pythonic way to implement a simple FSM?

一个人想着一个人 提交于 2019-12-03 04:28:58
问题 Yesterday I had to parse a very simple binary data file - the rule is, look for two bytes in a row that are both 0xAA, then the next byte will be a length byte, then skip 9 bytes and output the given amount of data from there. Repeat to the end of the file. My solution did work, and was very quick to put together (even though I am a C programmer at heart, I still think it was quicker for me to write this in Python than it would have been in C) - BUT, it is clearly not at all Pythonic and it

Convert finite state machine to regular expression

做~自己de王妃 提交于 2019-12-02 21:12:35
Is there a tool (or an algorithm) to convert a finite state machine into a regular expression ? (not the other way around, that would be easy). There are several algorithms to perform this task: the "state-elimination method" from Brzozowski and Mc Cluskey, the resolution of a system of linear equation, the method from McNaughton and Yamada, etc. They are very well described in Automata and rational expressions by Jacques Sakarovitch. The state-elimination method in particular is simple to understand. The key idea is that you are going to build an automaton labeled by rational (aka regular)

Designing high-performance State Machine in Java

不问归期 提交于 2019-12-02 19:29:42
I am in the process of starting to write a Java library to implement high-performance Finite State Machines. I know there are a lot of libraries out there, but I want to write my own from scratch, as almost all the libraries out there construct automatons optimized for handling only one at a time. I would like to know what the people in the SO community who have dabbled in state machine design feels are the most important / best design principles when it comes to implementing high-performance libraries like these. Considerations The automatons generated are typically not massive. (~ 100-500

VHDL: button debounce inside a Mealy State Machine

情到浓时终转凉″ 提交于 2019-12-02 19:04:27
问题 Hi I'm trying to implement a mealy machine using VHDL, but I'll need to debounce the button press. My problem is I'm not sure where should I implement the debouncing. My current work is like this: process(clk) begin if(clk' event and clk = '1') then if rst = '1' then curr_state <= state0; else curr_state <= next_state; end if; end if; end process; process(curr_state, op1,op0,rst) --here op1,op0 and rst are all physical buttons and I need to debounce op1 and op0 begin if rst = '1' then ...some

Graphical Finite State Machine Editor [closed]

谁都会走 提交于 2019-12-02 18:07:44
I am looking for a sophisticated graphical FSM editor that can export a model in a well-documented output format, like SCXML or similar. Can anybody recommend me a tool? I am only just now starting to look at YAKINDU - it looks like it might be a great graphical FSM tool built on top of the Eclipse framework, and has (IIUC) automatic code generation for the state graph. I found this pretty interesting software DRAKON is a visual language for specifications from the Russian space program. DRAKON is used for capturing requirements and building software that controls spacecraft. http://drakon

What is the Pythonic way to implement a simple FSM?

守給你的承諾、 提交于 2019-12-02 17:42:10
Yesterday I had to parse a very simple binary data file - the rule is, look for two bytes in a row that are both 0xAA, then the next byte will be a length byte, then skip 9 bytes and output the given amount of data from there. Repeat to the end of the file. My solution did work, and was very quick to put together (even though I am a C programmer at heart, I still think it was quicker for me to write this in Python than it would have been in C) - BUT, it is clearly not at all Pythonic and it reads like a C program (and not a very good one at that!) What would be a better / more Pythonic

VHDL: button debounce inside a Mealy State Machine

怎甘沉沦 提交于 2019-12-02 10:35:26
Hi I'm trying to implement a mealy machine using VHDL, but I'll need to debounce the button press. My problem is I'm not sure where should I implement the debouncing. My current work is like this: process(clk) begin if(clk' event and clk = '1') then if rst = '1' then curr_state <= state0; else curr_state <= next_state; end if; end if; end process; process(curr_state, op1,op0,rst) --here op1,op0 and rst are all physical buttons and I need to debounce op1 and op0 begin if rst = '1' then ...some implementation else ...implement the debounce logic first ...process some input case curr_state is

VHDL - FSM not starting (JUST in timing simulation)

一笑奈何 提交于 2019-12-01 13:41:13
I'm working for my master thesis and I'm pretty new to VHDL, but still I have to implement some complex things. This is one of the easiest structures I had to write, and still I'm encountering some problems. It's a FSM implementing a 24bit shift register with an active-low sync signal (to program a DAC). It's just the end of a complex elaboration chain I created for my project. I followed the example model of a FSM as much as I could. The behavioral simulation works fine, actually the whole elaboration chain I created works perfectly fine as far as the behavioral simulation concerns. However,

Why is {a^n a^n | n >= 0} regular?

半世苍凉 提交于 2019-12-01 11:53:38
I understand the reason and the proof why {a^n b^n | n >= 0} is NOT regular. Why is {a^nb^n | n >= 0} not regular? The solution of one of my exercises is: {a^n a^n | n >= 0} is regular. How can I prove this thesis? Grijesh Chauhan Yes, Language {a n a n | n >= 0} is a regular language . To proof that certain language is regular, you can draw its dfa/regular expression. And you can drive do for this language as follows: Because " a n a n for n >= 0 " is same as " a 2n for n >=0", and that is "set of all string contests of even number of symbol a " that is regular — regular expression for this

VHDL - FSM not starting (JUST in timing simulation)

五迷三道 提交于 2019-12-01 11:07:48
问题 I'm working for my master thesis and I'm pretty new to VHDL, but still I have to implement some complex things. This is one of the easiest structures I had to write, and still I'm encountering some problems. It's a FSM implementing a 24bit shift register with an active-low sync signal (to program a DAC). It's just the end of a complex elaboration chain I created for my project. I followed the example model of a FSM as much as I could. The behavioral simulation works fine, actually the whole