fpga

I've written some Linux device drivers but I am still at the level of newbie hack. I can get them working but that's all I can claim. So far, I've been able to work them into a model of write data using write() and read data using read(). I occasionally use ioctl for more fine-tuned control. Now I want to build a coprocessing block in FPGA logic and write a device driver for the ARM processor in that same FPGA to offload work from the ARM to the FPGA. I'm having a hard time working out how best to design this interface. If access to the coprocessor was exclusive, data could be written to the

Is there a TAP ( Test Anything Protocol ) implementation for Verilog? It would be nice because then I could use prove to check my results automatically. Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time. 10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary. DaveParillo I don't think there is a native TAP implementation

cmd_register: process (rst_n, clk) begin if (rst_n='0') then cmd_r<= (others=>'0'); elsif (clk'event and clk='1') then cmd_r<=...; end if; end process cmd_register; I know "<=" specifies assignment but what is others ? And what does => do? cmd_r is defined as a std_logic_vector , or unsigned or signed signal. let's see how this signal type are defined: type std_logic_vector is array (natural range <>) of std_logic; type unsigned is array (natural range <>) of std_logic; type signed is array (natural range <>) of std_logic; Note that these 3 types have the same definition as an array of std

-------1、 SCK信号线只由主设备控制，从设备不能控制信号线。同样，在一个基于SPI的设备中，至少要有一个主控设备。这样传输的特点：此传输方式有一个优点，与普通串行通信不同，普通的串行通信一次连续传送至少8位数据，而SPI允许数据一位一位的传送，甚至允许暂停，因为SCK时钟线由主控设备控制，当没有时钟跳变时，从设备不采集或传送数据。也就是说，主设备通过对SCK时钟线的控制可以完成对通信的控制。SPI协议还可以实现数据的交换：因为SPI的数据输入和输出线独立所以允许同时完成数据的输入和输出。不同的SPI设备的实现方式不尽相同，主要时改变和采集数据的时间不同，在时钟信号上升沿或下降沿采集有不同的定义 来源： https://www.cnblogs.com/ArChieve/p/11854134.html

is there any function in VHDL which is used to get current simulation time at which a process is running? May be same like the function in systemC sc_time_stamp() Yes there is. Use the keyword now . You can print the simulation time using VHDL Attributes: report "current time = " & time'image(now); You can also store the current time to a variable: variable v_TIME : time := 0 ns; v_TIME := now; -- STUFF HAPPENS v_TIME := now - V_TIME; --used to find delta time If you want to know the time within your synthesised design, you will have to manage that yourself. For example, a free-running counter

I am new with Eclipse, I have used it for SW development and in Altra environment for Nios processor. But now, I have a pretty large project that I have to manage and I would like to use Eclipse to have all the files in the system to make it easier to manage and update. The project has multiple directories for various IPs and has multiple targets for ASCI, Xilinx and Altera FPGAs. In a near future the project will support both NIOS, Microblaze and ARM processors and I would really like to keep the whole project in one Eclipse project file if possible. I have tried several different options,

I am in the process of writing some Verilog modules for an FPGA design. I looked around the internet to find out how I best parametrize my modules. I see two different methods occurring often. I included an example hereunder of the two different methodologies. Which of these methods is the best way to parametrize modules? What is the difference? Is it vendor-dependent (Altera vs Xilinx)? The first method: Module definition: module busSlave #(parameter DATA_WIDTH = 1) ( input [DATA_WIDTH-1:0] bus_data, input bus_wr, ... ); endmodule Module instantiation: module top; //DATA_WIDTH is 32 in this

I am trying to use fixed point numbers in my VHDL project, but I keep having trouble implementing the library (found here http://www.eda-stds.org/fphdl/fixed_pkg_c.vhdl ). The error I receive when trying to simulate is this <ufixed> is not declared My question is how exactly should a library be implemented so it can be used? As of now I have added it to the project in the IEEE_PROPOSED library, but it is not working. All source code can be found here https://github.com/srohrer32/beamformer/tree/fixed_num , under the hdl folder and libraries folder. Are you using modelsim? Are you using a