TAP (Test Anything Protocol) module for Verilog or SystemVerilog

Question

Is there a TAP (Test Anything Protocol) implementation for Verilog? It would be nice because then I could use prove to check my results automatically.

Update: 10/9/09: It was asked why not use assertions. Partly TAP gives me some good reporting such as number of files and number of tests. It also can be used with smolder for reporting of progress over time.

10/12/09: I'm looking for a minimal implentation with number of tests at the beginning and end and the ok, diag and fail functions. is() would really nice, but not necessary.

Answer 1

I don't think there is a native TAP implementation for Verilog. I would say that the whole point to using TAP is that adding a TAP generator is relatively straightforward. If you plan to do a lot of work in Verilog, you may want to write your own.

That said, have you looked at veripool? You may be able to use Verilog::Parser as a bridge to generate TAP output you could consume with TAP::Parser & Test::Harness.