cpu

When I run a single-threaded program that i have written on my quad core Intel i can see in the Windows Task Manager that actually all four cores of my CPU are more or less active. One core is more active than the other three, but there is also activity on those. There's no other program (besided the OS kernel of course) running that would be plausible for that activitiy. And when I close my program all activity an all cores drops down to nearly zero. All is left is a little "noise" on the cores, so I'm pretty sure all the visible activity comes directly or indirectly (like invoking system

When my program performs a load operation with acquire semantics/store operation with release semantics or perhaps a full-fence, it invalidates the CPU's cache. My question is this: which part of the cache is actually invalidated? only the cache-line that held the variable that I've used acquire/release? or perhaps the entire cache is invalidated? (L1 + L2 + L3 .. and so on?). Is there a difference in this subject when I use acquire/release semantics, or when i use a full-fence? I'm not an expert on this, but I stumbled on this document, maybe it's helpful http://www.rdrop.com/users/paulmck

When stepping a program in Delphi 7, the CPU window sometimes pops up and then steps through that instructions. I find this an annoyance as I wish to only step Pascal Code. Does anyone know how to disable this CPU pop-up? I would not be sorry if this window never ever shows. It did not happen on Delphi 5 which was my previous IDE that I used for Delphi. I do use the Step-Over button mostly and only step-into when wanting to get into detail of a used (pascal) unit. Lars Truijens Delphi does not, by default, step into the CPU window. So the answer to your question is not that it can not be done.

There are many different types of traps listed in processor datasheets, e.g. BusFault, MemManage Fault, Usage Fault and Address Error. What is their purpose? How can they be utilized in fault handling? Traps are essentially subroutine calls that are forced by the processor when it detects something unusual in your stream of instructions. (Some processors make them into interrupts, but that's mostly just pushing more context onto the stack; this gets more interesting if the trap includes a switch between user and system address spaces). This is useful for handling conditions that occur rarely

Closed. This question is off-topic. It is not currently accepting answers. Learn more . Want to improve this question? Update the question so it's on-topic for Stack Overflow. I used adb shell to get cpu used by my android app. and I recorded these values but I see in some cases cpu usage -for my app- 25%. my question is: is this value -25% from cpu- very high or what? and what ideal cpu % for android app? thanks in advance The first thing to remember is that when an app runs, it doesn't actually do computation for the whole time it's running: most of the time it's idle, waiting for data to

Is there any way to catch the L3-cache hits and misses by perf tool in Linux. According to the output of perf list cache , L1 and LLC cache are supported. According to the definition of perf_evsel__hw_cache array in perf's source code: const char *perf_evsel__hw_cache[PERF_COUNT_HW_CACHE_MAX] [PERF_EVSEL__MAX_ALIASES] = { { "L1-dcache", "l1-d", "l1d", "L1-data", }, { "L1-icache", "l1-i", "l1i", "L1-instruction", }, { "LLC", "L2", }, { "dTLB", "d-tlb", "Data-TLB", }, { "iTLB", "i-tlb", "Instruction-TLB", }, { "branch", "branches", "bpu", "btb", "bpc", }, { "node", }, }; LLC is an alias to L2