cpu | 易学教程

Determining the independent CPU's (specified with affinity ID's) for building ATLAS

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问题 I'm trying to determine the independent CPU's (specified with affinity ID's) for building ATLAS on a linux machine with 4 Intel CPU's with hyperthreading (ubuntu 12.04). The reason I'm doing this is that the ATLAS manual says to use only the physical cores on machines with hyper threading, on how to achieve this it says: "...you can tell ATLAS to use only the real cores if you learn a little about your machine. Unfortunately, ATLAS cannot presently autodetect these features, but if you

About the RIDL vulnerabilities and the “replaying” of loads

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问题 I'm trying to understand the RIDL class of vulnerability. This is a class of vulnerabilities that is able to read stale data from various micro-architectural buffers. Today the known vulnerabilities exploits: the LFBs, the load ports, the eMC and the store buffer. The paper linked is mainly focused on LFBs. I don't understand why the CPU would satisfy a load with the stale data in an LFB. I can imagine that if a load hits in L1d it is internally "replayed" until the L1d brings data into an

What are the possibillities to get overall CPU percentage usage

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问题 I have the following question: In UWP, how can we get an overall CPU percentage usage, RAM usage,free RAM, Running process, etc? It's required for task manager in UWP. 回答1: Hi after doing some looking it doesn't seem as if you can get the device CPU, RAM and Free Ram or the Running Processes. You can get the CPU, memory as well as the memory limits for an application. You can get these through the following ways: RAM : This is accessed through the MemoryManager Class MemoryManager

Sandy-Bridge CPU specification

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问题 I was able to put together bits here and there about the Sandy Bridge-E architecture but I am not totally sure about all the parameters e.g. the size of the L2 cache. Can anyone please confirm they are all correct? My main source was the 64-ia-32-architectures-optimization-manual.pdf 回答1: On sandy bridge, each core has 256KB of L2 (see the datasheet, section 1.1). for 6 cores, that's 1.5MB, but since each core only accesses its own, it's better to always look at it as 256KB per core. Moreover

Set cpu affinity on a loadable linux kernel module

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问题 I need to create a kernel module that enables ARM PMU counters on every core in the computer. I have trouble setting the cpu affinity. Ive tried sched_get_affinity , but apparently, it only works for user space processes. My code is below. Any ideas? #define _GNU_SOURCE #include <linux/module.h> /* Needed by all modules */ #include <linux/kernel.h> /* Needed for KERN_INFO */ int init_module(void){ unsigned reg; /* enable user-mode access to the performance counters*/ asm volatile("MRC p15, 0,

Why does it take so many instructions to run an empty program?

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问题 So recently I learned about the perf command in linux. I decided to run some experiments, so I created an empty c program and measured how many instructions it took to run: echo 'int main(){}'>emptyprogram.c && gcc -O3 emptyprogram.c -o empty perf stat ./empty This was the output: Performance counter stats for './empty': 0.341833 task-clock (msec) # 0.678 CPUs utilized 0 context-switches # 0.000 K/sec 0 cpu-migrations # 0.000 K/sec 112 page-faults # 0.328 M/sec 1,187,561 cycles # 3.474 GHz 1

How to know the values of CR registers from linux user and kernel modes

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I would like to know the CR0-CR4 register values on x86. Can I write inline assembly to read it out? Are there any other methods? (e.g., does OS keep any file structures to record these values) The Linux kernel has some function to read and write Control Registers, they are the read_crX and write_crX functions for the standard CR and xgetbv , xsetbv for the extended CR. User mode applications need a LKM to indirectly use these functions. In theory you just need to create a LKM with one or more devices and handle IO requests by reading or writing from CR. In practice you usually have more than

Which architecture to call Non-uniform memory access (NUMA)?

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问题 According to wiki: Non-uniform memory access (NUMA) is a computer memory design used in multiprocessing, where the memory access time depends on the memory location relative to a processor. But it is not clear whether it is about any memory including caches or about main memory only. For example Xeon Phi processor have next architecture: Memory access to main memory (GDDR) is same for all cores. Meanwhile memory access to L2 cache is different for different cores, since first native L2 cache

cpu_get_usage in php?

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问题 I have created a benchmark class that allows the user to insert for example $timer->checkpoint('1'); to check out some code for time,memory consumption and such.... and at the end of the code if she/he wants to test it she/he has to insert $result=$timer->result(); this gives out some data to public function result() like e.g. memory usage (using memory_get_peak_usage) and time consumption (microtime()). This all works just fine for me. But how can I use the combination of existing built-in

How do I find my CPU topology?

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问题 I am using Intel(R) Core(TM) i5 CPU M 560 @ 2.67GHz as I found out from cat /proc/cpuinfo . But I want to know exact hierarchy like how many sockets are there, and how many cores are there per socket and threads too, if supported. Any idea? 回答1: you can use command lscpu this will give information for processor related info dmidecode -t processor 回答2: lstopo from the hwloc package reports the info you want: Socket L#0 + L3 L#0 (6144KB) L2 L#0 (256KB) + L1 L#0 (32KB) + Core L#0 PU L#0 (P#0) PU