When can the CPU ignore the LOCK prefix and use cache coherency?
问题 I originally thought cache coherency protocols such as MESI can provide pseudo-atomicity but only across individual memory-load/store instructions. If I was performing a fetch, modify, write combination of instructions, MESI-alone wouldn't be able to enforce atomicity across the first instruction to the last. However, section 8 of the Intel reference manual Vol 3a says: 8.1.4 Effects of a LOCK Operation on Internal Processor Caches For the P6 and more recent processor families, if the area of