cpu

问题 I have been doing some experiments regarding measuring the latency of data transfer from CPU->GPU and GPU->CPU. I found that CPU->GPU data transfer rate is almost twice as much compared to GPU->CPU transfer rate for a particular message size. Can anybody explain me why this is so? 回答1: Since don't know the detail about your experiment, like what's CPU/GPU used, how to measure transfer rate, I just guess that, data transfer from CPU->GPU, normally is through DMA. each time it can transfer a

问题 CPU usage too high while running Ruta Script.So I plan to use GPU. Whether I need to do any additional process to run the script in GPU machine. Orelse is there any alternative solution to reduce the CPU usage Sample Script: PACKAGE uima.ruta.example; ENGINE utils.PlainTextAnnotator; TYPESYSTEM utils.PlainTextTypeSystem; WORDLIST EditorMarkerList = 'EditorMarker.txt'; WORDLIST EnglishStopWordList = 'EnglishStopWords.txt'; WORDLIST FirstNameList = 'FirstNames.txt'; WORDLIST

问题 I have written a program in C. Its a program created as result of a research. I want to compute exact CPU cycles which program consumes. Exact number of cycles. Any idea how can I find that? 回答1: The valgrind tool cachegrind ( valgrind --tool=cachegrind ) will give you a detailed output including the number of instructions executed, cache misses and branch prediction misses. These can be accounted down to individual lines of assembler, so in principle (with knowledge of your exact

问题 How can I detect which CPU is being used at runtime ? The c++ code needs to differentiate between AMD / Intel architectures ? Using gcc 4.2. 回答1: If you're on Linux (or on Windows running under Cygwin), you can figure that out by reading the special file /proc/cpuinfo and looking for the line beginning with vendor_id . If the string is GenuineIntel , you're running on an Intel chip. If you get AuthenticAMD , you're running on an AMD chip. void get_vendor_id(char *vendor_id) // must be at

问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 5 years ago . Nowadays, super-scalar RISC cpus usually support out-of-order execution, with branch prediction and speculative execution. They schedule work dynamically. What's the advantage of compiler instruction scheduling, compared to an out-of-order CPU's dynamic scheduling? Does compile-time static scheduling matter at

问题 I've recently read about CPU instruction reordering for efficiency. But I'm not able to understand how CPU reorders its instructions. I mean compile time reordering is thinkable since the compiler can foresee the upcoming code. But for a CPU which reads instruction one after the other, how does it see upcoming instructions to reorder them 回答1: Instructions are fetched in program order into an instruction queue; from the queue they are decoded and moved into reservation stations . These

问题 Ok, so I posted in In C# GetEnvironmentVariable("NUMBER_OF_PROCESSORS") returns the wrong number asking about how to get the correct number of cores in C#. Some helpful people directed me to a couple of questions where similar questions were asked but I have already tried those solutions. My question was then closed as being the same as another question, which is true, it is, but the solution given there didn't work. So I'm opening another one hoping that someone may be able to help realising

问题 Are there any way to determine or any resource where I can find the branch Target Buffer size for Haswell, Sandy Bridge, Ivy Bridge, and Skylake Intel processors? 回答1: Check Software optimization resources by Agner Fog, http://www.agner.org/optimize/ BTB should be in "The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers", http://www.agner.org/optimize/microarchitecture.pdf 3.7 Branch prediction in Intel Sandy Bridge and Ivy

问题 Recently I started to learn x86 assembly language and CPU architecture. I noticed that total number of int registers is 8, but for x86-64 it is 16. Why? There must be some explanation. 回答1: The x86 architecture has evolved from its earliest incarnation as an 8008 back in the early 1970s. At the time, memory bytes and therefore opcode space was extremely precious; only 3 bits were set aside for the (at the time) A, B, C, D, E, F, (and IIRC) H and L registers, all 8 bits. (I remember how

问题 I found this code on the web: package com.exercise.AndroidCPUinfo; import java.io.BufferedReader; import java.io.File; import java.io.FileReader; import java.io.IOException; import java.io.InputStream; import android.app.Activity; import android.os.Build; import android.os.Bundle; import android.widget.TextView; public class MainActivity extends Activity { /** * Called when the activity is first created. */ @Override public void onCreate(Bundle savedInstanceState) { super.onCreate