cpu-architecture

问题 I'm having a hard time understanding hyper-threading. If the logical core doesn't actually exist, what's the point of using hyper-threading?. The wikipedia article states that: For each processor core that is physically present, the operating system addresses two virtual (logical) cores and shares the workload between them when possible. If the two logical cores share the same execution unit, that means one of the threads will have to be put on hold while the other executes, that being said,

问题 I'm having a hard time understanding hyper-threading. If the logical core doesn't actually exist, what's the point of using hyper-threading?. The wikipedia article states that: For each processor core that is physically present, the operating system addresses two virtual (logical) cores and shares the workload between them when possible. If the two logical cores share the same execution unit, that means one of the threads will have to be put on hold while the other executes, that being said,

问题 I want to look into how latest processors differs from standard RISC V implementation (RISC V having 5 stage pipeline - fetch, decode, memory , ALU , Write back) but not able to find how should I start approaching the problem so as to find the current implementation of pipelining at processor I tried referring Intel documentation for i7-4510U documentation but it was not much help 回答1: Haswell's pipeline length is reportedly 14 stages (on a uop-cache hit), 19 stages when fetching from L1i for

问题 Larger memories have higher decoding delay; why is the register file a part of the memory then? Does it only mean that the registers are "mapped" SRAM registers that are stored inside the microprocessor? If not, what would be the benefit of using registers as they won't be any faster than accessing RAM? Furthermore, what would be the use of them at all? I mean these are just a part of the memory so I don't see the point of having them anymore. Having them would be just as costly as

问题 Larger memories have higher decoding delay; why is the register file a part of the memory then? Does it only mean that the registers are "mapped" SRAM registers that are stored inside the microprocessor? If not, what would be the benefit of using registers as they won't be any faster than accessing RAM? Furthermore, what would be the use of them at all? I mean these are just a part of the memory so I don't see the point of having them anymore. Having them would be just as costly as

问题 Larger memories have higher decoding delay; why is the register file a part of the memory then? Does it only mean that the registers are "mapped" SRAM registers that are stored inside the microprocessor? If not, what would be the benefit of using registers as they won't be any faster than accessing RAM? Furthermore, what would be the use of them at all? I mean these are just a part of the memory so I don't see the point of having them anymore. Having them would be just as costly as

问题 I have built a Winforms .NET Core app that I want to submit to the Windows Store. In line with that goal, I was able to create an app package from the answer here. Now I want to get my app onto the App Store. Following the steps here, it tells me that if I "created the package by using Visual Studio" I should, "Set the packaging project as the startup project, and then press F5 to start your app." So I did that, but got this err msg: Error MSB3270 There was a mismatch between the processor

问题 In the book "Computer Architecture", by Hennessy/Patterson, 5th ed, on page 360 they describe MSI protocol, and write something like: If the line is in state "Exclusive" (Modified), then on receiving "Write Miss" from the bus the current CPU 1) writes back the line into the bus, and then 2) goes into "Invalid" state. Why do we need to write-back the line, if it will be overwritten anyway by the successive write by the other CPU? Is it connected with the fact that every CPU should see the same

问题 In the book "Computer Architecture", by Hennessy/Patterson, 5th ed, on page 360 they describe MSI protocol, and write something like: If the line is in state "Exclusive" (Modified), then on receiving "Write Miss" from the bus the current CPU 1) writes back the line into the bus, and then 2) goes into "Invalid" state. Why do we need to write-back the line, if it will be overwritten anyway by the successive write by the other CPU? Is it connected with the fact that every CPU should see the same

问题 The L1/L2 cache are inclusive in Intel and L1 / L2 cache is 8 way associativity, means in a set there are 8 different cache lines exist. The cache lines are operated as a whole, means if I want to remove few bytes from a cache line, the whole cache line will be removed , not the only those bytes which I want to remove. Am I right ? Now, my question is whenever a cache line of a set is removed/evicted from cache, either by some other process or by using clflush(manual eviction of a cache line