cpu-architecture

问题 I'm a student doing some research on Hyper-threading recently. I'm a little confused about the feature - L1 Data Cache Context Mode. In the architecture optimization manual, it was described that L1 cache can operate in two modes: The first level cache can operate in two modes depending on a context-ID bit: Shared mode: The L1 data cache is fully shared by two logical processors. Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical

问题 I'm a student doing some research on Hyper-threading recently. I'm a little confused about the feature - L1 Data Cache Context Mode. In the architecture optimization manual, it was described that L1 cache can operate in two modes: The first level cache can operate in two modes depending on a context-ID bit: Shared mode: The L1 data cache is fully shared by two logical processors. Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical

问题 Some CPUs (notably x86 CPUs) feature a parity flag on their status register. This flag indicates whether the number of bits of the result of an operation is odd or even. What actual practical purpose does the parity flag serve in a programming context? Side note: I'm presuming it's intended to be used in conjunction with a parity bit in order to perform basic error checking, but such a task seems to uncommon to warrant an entire CPU flag. 回答1: Back in the "old days" when performance was

问题 Some CPUs (notably x86 CPUs) feature a parity flag on their status register. This flag indicates whether the number of bits of the result of an operation is odd or even. What actual practical purpose does the parity flag serve in a programming context? Side note: I'm presuming it's intended to be used in conjunction with a parity bit in order to perform basic error checking, but such a task seems to uncommon to warrant an entire CPU flag. 回答1: Back in the "old days" when performance was

问题 Some CPUs (notably x86 CPUs) feature a parity flag on their status register. This flag indicates whether the number of bits of the result of an operation is odd or even. What actual practical purpose does the parity flag serve in a programming context? Side note: I'm presuming it's intended to be used in conjunction with a parity bit in order to perform basic error checking, but such a task seems to uncommon to warrant an entire CPU flag. 回答1: Back in the "old days" when performance was

问题 Most CPU architectures will re-order stores-load operations, but my question is why? My interpretation of a store-load barrier would look like this: x = 50; store_load_barrier; y = z; Furthermore, I don't see how this barrier would be have much use in lock-free programming in comparison to release and acquire semantics. 回答1: Short Answer : The store-load barrier prevents the processor from speculatively executing LOAD that come after a store-load barrier until all previous stores have

来源： https://stackoverflow.com/questions/40727700/why-implement-data-cache-and-instruction-cache-to-reduce-miss

来源： https://stackoverflow.com/questions/40727700/why-implement-data-cache-and-instruction-cache-to-reduce-miss

来源： https://stackoverflow.com/questions/40727700/why-implement-data-cache-and-instruction-cache-to-reduce-miss

来源： https://stackoverflow.com/questions/64810192/to-what-should-i-change-the-targeted-processor-architecture-of-my-project