cpu-architecture

I am trying to understand the concept of Rx and Tx descriptors used in Network driver code. Are Descriptors in software(RAM) or hardware (NIC card). How do they get filled. EDIT: So in a Realtek card driver code. I have a following struct defined. struct Desc { uint32_t opts1; uint32_t opts2; uint64_t addr; }; txd->addr = cpu_to_le64(mapping); txd->opts2 = cpu_to_le32(opts2); txd->opts1 = cpu_to_le32(opts1 & ~DescOwn); So are the opts1 and opts2 and there bits like DescOwn card specific? Will they be defined by the manufacturer in the datasheet? Thanks Nayan Quick Answer: They are software

As a school assignment, I need to find a way to get the L1 data cache line size, without reading config files or using api calls. Supposed to use memory accesses read/write timings to analyze & get this info. So how might I do that? In an incomplete try for another part of the assignment, to find the levels & size of cache, I have: for (i = 0; i < steps; i++) { arr[(i * 4) & lengthMod]++; } I was thinking maybe I just need vary line 2, (i * 4) part? So once I exceed the cache line size, I might need to replace it, which takes sometime? But is it so straightforward? The required block might

Program counter holds the address of the instruction that should be executed next, while instruction register holds the actual instruction to be executed. wouldn't one of them be enough? And what is the length of each one of these registers? Thanks. Haleeq Usman You will need both always. The program counter (PC) holds the address of the next instruction to be executed, while the instruction register (IR) holds the encoded instruction. Upon fetching the instruction, the program counter is incremented by one "address value" (to the location of the next instruction). The instruction is then

I am trying to profile and optimize algorithms and I would like to understand the specific impact of the caches on various processors. For recent Intel x86 processors (e.g. Q9300), it is very hard to find detailed information about cache structure. In particular, most web sites (including Intel.com ) that post processor specs do not include any reference to L1 cache. Is this because the L1 cache does not exist or is this information for some reason considered unimportant? Are there any articles or discussions about the elimination of the L1 cache? [edit] After running various tests and

Recently I've been reading some SO archives and encountered statements against the x86 architecture. Why do we need different CPU architecture for server & mini/mainframe & mixed-core? says " PC architecture is a mess, any OS developer would tell you that. " Is learning Assembly Language worth the effort? ( archived ) says " Realize that the x86 architecture is horrible at best " Any easy way to learn x86 assembler? says " Most colleges teach assembly on something like MIPS because it's much simpler to understand, x86 assembly is really ugly " and many more comments like "Compared to most

(a) You are given a memory system that has two levels of cache (L1 and L2). Following are the specifications: Hit time of L1 cache: 2 clock cycles Hit rate of L1 cache: 92% Miss penalty to L2 cache (hit time of L2): 8 clock cycles Hit rate of L2 cache: 86% Miss penalty to main memory: 37 clock cycles Assume for the moment that hit rate of main memory is 100%. Given a 2000 instruction program with 37% data transfer instructions (loads/stores), calculate the CPI (Clock Cycles per Instruction) for this scenario. For this part, I calculated it like this (am I doing this right?): (m1: miss rate of

I'm reading about the Instruction Decode (ID) phase in the MIPS datapath, and I've got the following quote: "Once operands are known, read the actual data (from registers) or extend the data to 32 bits (immediates)." Can someone explain what the "extend the data to 32 bits (immediates)" part means? I know that registers all contain 32 bits, and I know what an immediate is. I just don't understand why you need to extend the immediate from 26 to 32 bits. Thanks! On a 32-bit CPU, most of the operations you do (like adding, subtracting, dereferencing a pointer) are done with 32-bit numbers. When

We got a cache given with 8 frames and it's directly mapped. Following access sequence on main memory blocks has been observed: 2 5 0 13 2 5 10 8 0 4 5 2 Count the hit rate of this organized cache. Solution: I understand how and why the numbers are placed in the table like that. But I don't understand why 2 and 5 have been bold-printed and why we got hit rate of 17%. This has been solved by our professor but I don't understand it completely. Like was mentioned by @Margaret Bloom in the comments, the numbers in bold refer to cache-hits. Non-bold refer to cache misses. You might understand it