cpu-architecture

问题 Details about the X5650 processor at https://www.cpu-world.com/CPUs/Xeon/Intel-Xeon%20X5650%20-%20AT80614004320AD%20(BX80614X5650).html important notes: L3 cache size : 12288KB cache line size : 64 Consider the following two functions, which each increment the values in an array by 100. void incrementVector1(INT4* v, int n) { for (int k = 0; k < 100; ++k) { for (int i = 0; i < n; ++i) { v[i] = v[i] + 1; } } } void incrementVector2(INT4* v, int n) { for (int i = 0; i < n; ++i) { for (int k = 0

问题 This question comes in context of a section on virtual memory in an undergraduate computer architecture course. Neither the teaching assistants nor the professor were able to answer it sufficiently, and online resources are limited. Question: Suppose a processor with the following specifications: 8KB pages 32-bit virtual addresses 28-bit physical addresses a two-level page table, with a 1KB page table at the first level, and 8KB page tables at the second level 4-byte page table entries a 16

问题 This question comes in context of a section on virtual memory in an undergraduate computer architecture course. Neither the teaching assistants nor the professor were able to answer it sufficiently, and online resources are limited. Question: Suppose a processor with the following specifications: 8KB pages 32-bit virtual addresses 28-bit physical addresses a two-level page table, with a 1KB page table at the first level, and 8KB page tables at the second level 4-byte page table entries a 16

问题 Amdahl’s law states that a speed up of the entire system is an_old_time / a_new_time where the a_new_time can be represented as ( 1 - f ) + f / s’ , where f is the fraction of the system that is enhanced by some modification, and s’ is the amount by which that fraction of the system is enhanced. However, after solving this equation for s’ , it seems like there are many cases in which s’ is negative, which makes no physical sense. Taking the case that s = 2 (a 100% increase in the speed for

问题 I am trying to use cpu-frequency scaling to set cpu frequency. In my system, only powersave , performance frequency-scaling-governor supported. It was explained in other document, by default, intel_pstate is enabled and it only supports powersave , performance frequency-scaling-governor and solution is disable intel_pstate. So I tried to disable as below sudo nano /etc/default/grub GRUB_CMDLINE_LINUX_DEFAULT="intel_pstate=disable" sudo update-grub on reboot, intel_pstate is enabled. so ,

问题 I haven't found a clear answer: does the control unit itself fetch pre-defined instructions to execute a cache eviction, or does the operating system intervene? If so, how? 回答1: Which part of the computer manages cache replacement? Typically; a cache manages cache replacement itself (its not done by a separate part). There are many types of caches where some are implemented by software (DNS cache, web page cache, file data cache) and some are implemented in hardware (instruction caches, data

问题 I have recently been interested in understanding low level computing. I understand that today's widely used computers follow x86/x86-64 architecture. To my understanding, architecture, more specifically Instruction Set Architecture (ISA) is the set of instructions that the programmer is able to issue to the CPU. The first question, Is the ISA keeps evolving or remains the same? I think that it keeps evolving (meaning new instructions keeps getting added/previous instructions modified?) but

问题 I have recently been interested in understanding low level computing. I understand that today's widely used computers follow x86/x86-64 architecture. To my understanding, architecture, more specifically Instruction Set Architecture (ISA) is the set of instructions that the programmer is able to issue to the CPU. The first question, Is the ISA keeps evolving or remains the same? I think that it keeps evolving (meaning new instructions keeps getting added/previous instructions modified?) but

问题 From the naming and this article I feel the answer is no, but I don't understand why. The bottleneck is how fast you can fetch data from memory. Whether you can fetch instruction at the same time doesn't seem to matter. Don't you still have to wait until the data arrive? Suppose fetching data takes 100 cpu cycles and executing instruction takes 1, the ability of doing that 1 cycle in advance doesn't seem to be a huge improvement. What am I missing here? Context: I came across this article

问题 This question already has answers here : The advantages of using 32bit registers/instructions in x86-64 (2 answers) Intel X86 Assembly: How to tell many bits wide is an argument? (1 answer) x86 find out operand size of instruction given only the hex machine code? (2 answers) Why is default operand size 32 bits in 64 mode? (1 answer) 64 bit assembly, when to use smaller size registers (5 answers) Closed 3 months ago . I'm learning (slowly and painfully) about x86-64 instructions, and found