cpu-architecture

问题 We had quite an annoying issue that started about a month ago, where we could add a controller in an MVC project which required automatic code generation/scaffolding. We figured out today that it was something to do with the platform. Originally, it was set to Any CPU which to me seems the correct setting. However, we set it to x86 as the version of Visual Studio we have is 32-Bit, and we were able to add controllers again. Added a controller, built, and went to view the application and it

问题 The description of the RESOURCE_STALLS.RS hardware performance event for Intel Broadwell is the following: This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend

问题 Is there a relation between endianness of a processor and the direction of stack growth? For example, x86 architecture is little endian and the stack grows downwards (i.e. it starts at highest address and grows towards lower address with each push operation). Similarly, in SPARC architecture , which is big endian , the stack starts at lowest address and grows upwards towards higher addresses. This relationship pattern is seen in almost all architectures. I believe there must be a reason for

问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 5 years ago . Nowadays, super-scalar RISC cpus usually support out-of-order execution, with branch prediction and speculative execution. They schedule work dynamically. What's the advantage of compiler instruction scheduling, compared to an out-of-order CPU's dynamic scheduling? Does compile-time static scheduling matter at

问题 Are there any way to determine or any resource where I can find the branch Target Buffer size for Haswell, Sandy Bridge, Ivy Bridge, and Skylake Intel processors? 回答1: Check Software optimization resources by Agner Fog, http://www.agner.org/optimize/ BTB should be in "The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers", http://www.agner.org/optimize/microarchitecture.pdf 3.7 Branch prediction in Intel Sandy Bridge and Ivy

问题 I am running jobs on a cluster composed of machines with different architectures: gcc -march=native -Q --help=target | grep -- '-march=' | cut -f3 gives me one of these: broadwell , haswell , ivybridge , sandybridge or skylake . The executable needs to be the same, so I cannot use -march=native but at the same time the architectures have things in common (I think they all support AVX?). I am aware that gcc (contrary to Intel icc ) does not allow for multiple archictures in a single executable

问题 Since we have three assemblies that come in explicit x86 and x64 versions, I've edited the corresponding .csproj file(s) to use, for example, a block like this: <ItemGroup Condition=" '$(Platform)' == 'x86' "> <Reference Include="CaliberRMSDK"> <HintPath>..\Libraries\CaliberRMSDK_IKVM\32bit\CaliberRMSDK.dll</HintPath> </Reference> <Content Include="..\Libraries\CaliberRMSDK_IKVM\32bit\ikvm-native.dll"> <Link>ikvm-native.dll</Link> <CopyToOutputDirectory>Always</CopyToOutputDirectory> <

问题 I'm currently wring a Cocoa application which needs to execute some (console) applications which are optimized for 32 and 64 bit. Because of this I would like to detect what CPU architecture the application is running on so I can start the correct console application. So in short: how do I detect if the application is running on a 64 bit OS? Edit: I know about the Mach-O fat binaries, that was not my question. I need to know this so I can start another non bundled (console) application. One

问题 In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11. There is four types of instruction formats R, I, S, and U, then there is a variants of S and U types which are SB and UJ which I suppose mean Branch and Jump as shown in figure 2.3. Then there is the types of Immediate produced by RISC-V instructions shown in figure 2.4. So my questions are, why the SB and UJ are needed? and why shuffle the Immediate bits in that way?

问题 I was just thinking, how do machines interpreter binary code? All I understand is your code get's turned into 1 and 0's so the machine can understand them, but how do they do that? Is it just a normal text to binary translation? 回答1: First, "binary" doesn't mean what you think it means (any data on the computer, including text is already binary, it just the way we decide to display and handle is different). Second, compilation is not a simple transformation to funny characters (if it were, we