cpu-architecture

问题 Can someone very briefly point out the differences between the memory bus and address bus in computer architectures ? Also when you say memory bus does it imply that you are referring to the databus ? 回答1: Beautifully explained here. In isolation, the microprocessor, the memory and the input/output ports are interesting components, but they cannot do anything useful. In combination, they can form a complete system if they can communicate with each other. This communication is accomplished

问题 I'm trying to re-implement malloc and I need to understand the purpose of the alignment. As I understand it, if the memory is aligned, the code will be executed faster because the processor won't have to take an extra step to recover the bits of memory that are cut. I think I understand that a 64-bit processor reads 64-bit by 64-bit memory. Now, let's imagine that I have a structure with in order (without padding): a char, a short, a char, and an int. Why will the short be misaligned? We have

问题 I'm trying to re-implement malloc and I need to understand the purpose of the alignment. As I understand it, if the memory is aligned, the code will be executed faster because the processor won't have to take an extra step to recover the bits of memory that are cut. I think I understand that a 64-bit processor reads 64-bit by 64-bit memory. Now, let's imagine that I have a structure with in order (without padding): a char, a short, a char, and an int. Why will the short be misaligned? We have

问题 I have an application which has 2 threads , thread A affinity to core 1 and thread B affinity to core 2 , core 1 and core 2 are in the same x86 socket . thread A do a busy spin of integer x , thread B will increase x under some conditions , When thread B decide to increase x , it invalidate the cache line where x located ,and according to x86 MESI protocal , it store new x to store buffer before core2 receive invalidate ack, then after core2 receive invalidate ack , core2 flush store buffer .

问题 How can i change my code to make it work on sms32v50? .data #storing data startmsg: .asciiz "Pick a number between 1 and 100.\n\n" guessmsg: .asciiz "Enter your guess\n" tooHigh: .asciiz "Your guess is too high.\n\n" tooLow: .asciiz "Your guess is too low.\n\n" wingame: .asciiz "You have guessed the number. Well done!\n\n" .text #start of program start: jal random add $t0, $zero, $a0 # store random number $a0 in $t0 li $v0, 4 # print string la $a0, startmsg syscall ###########################

问题 I am not able to understand the difference between Instruction set and Instruction set architecture. I know what is an instruction set . Instruction set just defines the possible instructions we can give to the processor and how the instruction are give ( therefore the instruction format ) to the processor. Now what is Instruction set architecture ? I have looked up wikipedia, it has a page on instruction set and inside it, on the first line there is a link to instruction set architecture

问题 I am not able to understand the difference between Instruction set and Instruction set architecture. I know what is an instruction set . Instruction set just defines the possible instructions we can give to the processor and how the instruction are give ( therefore the instruction format ) to the processor. Now what is Instruction set architecture ? I have looked up wikipedia, it has a page on instruction set and inside it, on the first line there is a link to instruction set architecture

问题 I'm going though 'Computer Systems: A Programmer's Perspective', chapter 3 which is about machine-level representation. I'm currently on 'Arithmetic and Logic Operations', doing one of the practice problem. The problem gives C code fragment: short scale3(short x, short y, short z){ short t = ----------------; return t; } additionally i'm given an assembly code, generated from the COMPLETE code in scale3 function: scale3: leaq (%rsi, %rsi, 9), %rbx leaq (%rbx, %rdx), %rbx leaq (%rbx, %rdi,

问题 I'm going though 'Computer Systems: A Programmer's Perspective', chapter 3 which is about machine-level representation. I'm currently on 'Arithmetic and Logic Operations', doing one of the practice problem. The problem gives C code fragment: short scale3(short x, short y, short z){ short t = ----------------; return t; } additionally i'm given an assembly code, generated from the COMPLETE code in scale3 function: scale3: leaq (%rsi, %rsi, 9), %rbx leaq (%rbx, %rdx), %rbx leaq (%rbx, %rdi,

问题 Reading about the virtualized page table concept, where part of the page table is put in virtual memory. Wikipedia as well as Patterson & Hennessy (5.7 elaboration in the Page Faults section) say that the reason you don't put the entire page table into virtual memory is that it can lead to circular page faults. But it seems to me like there's an even more basic issue - how you would find the page table in the first place? It seems like you necessarily need some record of where in physical