cpu-architecture

问题 First I am a little bit confused with the differences between movq and movabsq , my text book says: The regular movq instruction can only have immediate source operands that can be represented as 32-bit two’s-complement numbers. This value is then sign extended to produce the 64-bit value for the destination. The movabsq instruction can have an arbitrary 64-bit immediate value as its source operand and can only have a register as a destination. I have two questions to this. Question 1 The

问题 I read that x86 CPUs have a variable instruction length of 1 to 15 bytes. On the other hand, it is also written that the x86 word size is 32 bits, that means all registers, including the instruction register which holds the actual instruction, are 32 bits wide (4 Bytes). That means the instructions can be wider than the instruction register. How does this fit? Further more, I learned that after executing an instruction, without jumping, the instruction counter is incremented by 4. That means

问题 I read that x86 CPUs have a variable instruction length of 1 to 15 bytes. On the other hand, it is also written that the x86 word size is 32 bits, that means all registers, including the instruction register which holds the actual instruction, are 32 bits wide (4 Bytes). That means the instructions can be wider than the instruction register. How does this fit? Further more, I learned that after executing an instruction, without jumping, the instruction counter is incremented by 4. That means

问题 Intel pushed microcode update to fix error called "Jump Conditional Code (JCC) Erratum". The update microcode caused some operation to be inefficient due to disabling putting code to ICache under certain conditions. Published document, titled Mitigations for Jump Conditional Code Erratum lists not only JCC , it lists: unconditional jumps, conditional jumps, macro-fused conditional jumps, calls, and return. MSVC switch /QIntel-jcc-erratum documentation mentions: Under /QIntel-jcc-erratum, the

问题 I am somewhat confused with what how cache coherence systems function in modern multi core CPU. I have seen that snooping based protocols like MESIF/MOESI snooping based protocols have been used in Intel and AMD processors, on the other hand directory based protocols seem to be a lot more efficient with multiple core as they don't broadcast but send messages to specific nodes. What is the modern cache coherence solution in AMD or Intel processors, is it snooping based protocols like MOESI and

问题 Register variables are a well-known way to get fast access ( register int i ). But why are registers on the top of hierarchy (registers, cache, main memory, secondary memory)? What are all the things that make accessing registers so fast? 回答1: Registers are a core part of the CPU, and much of the instruction set of a CPU will be tailored for working against registers rather than memory locations. Accessing a register's value will typically require very few clock cycles (likely just 1), as

问题 I'm a little confused by the meaning of "Aliasing" between CPU-cache and Physical address . First I found It's definition on Wikipedia : However, VIVT suffers from aliasing problems, where several different virtual addresses may refer to the same physical address . Another problem is homonyms, where the same virtual address maps to several different physical addresses. but after a while I saw a different definition on a presentation( ppt ) of DAC'05: "Energy-Efficient Physically Tagged Caches

问题 I am trying to calculate the maximum memory size knowing the bit length of an address and the size of the memory cell. It is my understanding that if the address is n bits then there are 2^n memory locations. But then to calculate the actual memory size of the machine, you would need to multiply the number of addresses by the size of the memory cell. Is that correct? To put it another way, Step 1: calculate the length of the address in bits (n bits) Step 2: calculate the number of memory

问题 Consider a computer system with a 32-bit logical address and 4KB page size. The system supports up to 512MB of physical memory. How many entries are there in a conventional single-level page table? Conventional single-level page table: 2^32 / 2^12 (4000) = 2^20 = 1,048,576 Why did I have to divide 2^32 / 2^12 to get the answer? How many entries are there in an inverted page table? An inverted page table needs as many entries as there are page frames in memory. Inverted page table: 2^29 (512mb

问题 I was doing a question on Computer Architecture and in it it was mentioned that the cache is a split cache, and no hazard what does this exactly means? 回答1: Introduction A split cache is a cache that consists of two physically separate parts, where one part, called the instruction cache, is dedicated for holding instructions and the other, called the data cache, is dedicated for holding data (i.e., instruction memory operands). Both of the instruction cache and data cache are logically