Makefile C subdirectory rule to make obj
问题 I am running a simple Makefile with no problems: CC=gcc CFLAGS= -std=c99 -ggdb -Wall -I. DEPS = hellomake.h OBJ = hellomake.o hellofunc.o %.o: %.c $(DEPS) $(CC) -c -o $@ $< $(CFLAGS) hellomake: $(OBJ) gcc -o $@ $^ $(CFLAGS) The files are in the main project's directory: ./project/Makefile ./project/hellomake.c ./project/hellomake.h Then I tried to organized the files, and put things like: ./project/Makefile ./project/src/hellomake.c ./project/include/hellomake.h and extra subdirectories