Verilog bit change location
Assuming I have a register reg [15:0] my_reg , which contains a 16-bit signed sample: How can I find the place where the first bit change is located? Meaning, that if assuming that my_reg = 16'b0001011011010111 , how can I know that the first change from 0 to 1 is at my_reg [12] ? Same for numbers starting with 1 ,negative numbers, e.g. my_reg = 16'b1111011011010111 would be interested in the position of the first appearing 0 (which is 11 in this case). The ultimate goal (to add a little bit of context) is to implement a digital FPGA built-in automatic gain control (AGC). Guy Same technique as