问题
I am a new bee in VHDL coding. I am currently working on starter kit spartan 3e. I have written a code for transmitting 5 bytes to PC and receiving 4 bytes. Now I have to add fifo buffer before transmitting and after receiving bytes.I have written code( taken from Pong P Chu) also but not working. Its taking too much time for synthesis. Please tell me where I am going wrong. Thanks in advance.
entity fifo is
generic (
B : natural :=32; --------------------------------------------------- number of bits
W : natural := 16 ----------------------------------------------------number of address bits
);
port ( ck : in std_logic; ------------ clock
reset : in std_logic;
rd : in std_logic; -------- control signal for read
wr : in std_logic; -------- control signal for write
-- btn0 : in std_logic;
write_data : in std_logic_vector ( B-1 downto 0); ----------------------------data to be written in FIFO
read_data : out std_logic_vector ( B-1 downto 0) :=( others=> '0');------------------------------ data read from FIFO
empty : out std_logic; ------------ shows FIFO is empty, cannot be read
full : out std_logic ------------ shows FIFO is full, cannot be written
);
end fifo;
architecture arch4 of fifo is
--------------state machines declared----------------------
type reg_file_type is array (2**W - 1 downto 0) of std_logic_vector (B-1 downto 0); --------------------array of 32 cross 32 for data
signal array_reg : reg_file_type;
--------------------------------------------------------------------
----variables-------------------------------------------------------
--signal read_data : std_logic_vector ( B-1 downto 0); ------------------------------ data read from FIFO
signal write_ptr_reg : std_logic_vector (W-1 downto 0); ----- addressing the data in fifo to write
signal write_ptr_next: std_logic_vector (W-1 downto 0); ----- addressing next data in fifo to write
signal write_ptr_succ : std_logic_vector (W-1 downto 0); ---- addressing next to next data in fifo to write
signal read_ptr_reg : std_logic_vector (W-1 downto 0); ----- addressing the data in fifo to read
signal read_ptr_next: std_logic_vector (W-1 downto 0); ----- addressing next data in fifo to read
signal read_ptr_succ : std_logic_vector (W-1 downto 0); ---- addressing next to next data in fifo to read
signal write_operation : std_logic_vector (1 downto 0); ---- 00,01,10,11 only 00,01 and 10 are valid
signal write_enable : std_logic ; ---------------- write enable
-- signal rd : std_logic; -------- control signal for read
-- signal wr : std_logic; -------- control signal for write
--signal empty : std_logic; ------------ shows FIFO is empty, cannot be read
--signal full : std_logic ;------------ shows FIFO is full, cannot be written
signal full_reg : std_logic ;
signal empty_reg : std_logic ;
signal full_next : std_logic ;
signal empty_next : std_logic ;
egin
------------------------------------------initialising register ------------------------------------------------------
process (ck, reset)
begin
if (reset = '1') then
array_reg <= ( others => (others=> '0')); ---------------------initialsing
else
if rising_edge(ck) then
if write_enable ='1' then
--array_reg (std_logic_vector(write_ptr_reg)) <= write_data;
array_reg (CONV_INTEGER( unsigned(write_ptr_reg))) <= write_data; -------------------------- directed towards address for writing data (first position)
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------------------------------------
--read_data <= array_reg (std_logic_vector(read_ptr_reg)) ;
read_data <= array_reg (CONV_INTEGER( unsigned(read_ptr_reg))) ; ------ directed towards address for reading data (first position)
write_enable <= wr and ( not full_reg ); ------ write enabled only when FIFO is not full
---============================ control logic for fifo==================================================
--------------------reading and writing process with address pointers
--======================================================================================================
process (ck, reset)
begin
if (reset = '1') then
write_ptr_reg <= (others => '0');
read_ptr_reg <= (others => '0');
full_reg <= '0';
empty_reg <='1';
else
if rising_edge(ck) then
write_ptr_reg <= write_ptr_next; ---- control of pointers
read_ptr_reg <= read_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end if;
end if;
end process;
------======================= successive pointer values update--=====================================
write_ptr_succ <= std_logic_vector(( write_ptr_reg)+1);
read_ptr_succ <= std_logic_vector ((read_ptr_reg)+1);
---==========main process for read write operation, shifting pointers and checking status of fifo ====================
write_operation <= wr & rd ; ----- concatinating two signals so 10 or 01 is valid states
process (write_ptr_reg, write_ptr_succ, read_ptr_reg, read_ptr_succ,write_operation, empty_reg, full_reg)
begin
write_ptr_next <= write_ptr_reg;
read_ptr_next <= read_ptr_reg;
full_next <= full_reg;
empty_next <= empty_reg;
case write_operation is
when "00" =>
------------------------ wr =0 and read = 0 , no operation
when "01" =>
----------------------------- wr =0 and read = 1 , read operation
--if state_button = transit_pressed then
if (empty_reg /= '1') then ----------------not empty
read_ptr_next <= read_ptr_succ; ---- updating the address pointers
full_next <= '0'; ------ clearing full status
if (read_ptr_succ = write_ptr_reg) then ---- checking the pointer positions whether equal
empty_next <= '1';
end if;
end if;
-- end if;
when "10" =>
------------------------ wr =1 and read = 0, write operation
if (full_reg /= '1') then ---------- not full
write_ptr_next <= write_ptr_succ;---- updating the address pointers
empty_next <= '0'; --- clearing empty status
if ( write_ptr_succ = read_ptr_reg) then ------------- checking the pointer positions of successors to read pointer whether it is same or not
full_next <= '1'; -------------- fifo full only above condition is true
end if;
end if;
when others =>
------------------------------write and read i.e for 11
write_ptr_next <= write_ptr_succ;
read_ptr_next <= read_ptr_succ;
end case;
end process;
----- updating the flag
full <= full_reg;
empty <= empty_reg;
end architecture arch4;
回答1:
The design is too big, it can't fit any Spartan-3E device even if all memory is mapped to Block RAMs. Indeed there are 2097152 flip-flops for array_reg signal.
2**W = 2**16 = 65536
65536*B = 65536*32 = 2097152
The size of the FIFO should be reduced and it's better to use Block RAMs instead of flip-flops. Here is a RAM module in VHDL, which can be mapped to Block RAMs by Xilinx tools.
来源：https://stackoverflow.com/questions/44647825/during-implementing-fifo-buffer-code-for-serial-communication-taking-too-much-ti