问题:

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.

I take Gcd source code given on official web page of chisel.

  import chisel3._    class GCD extends Module {   val io = IO(new Bundle {     val a  = Input(UInt.width(32))     val b  = Input(UInt.width(32))     val e  = Input(Bool())     val z  = Output(UInt.width(32))     val v  = Output(Bool())   })   val x = Reg(UInt.width( 32))   val y = Reg(UInt.width( 32))   when (x > y)   { x := x -% y }   .otherwise     { y := y -% x }   when (io.e) { x := io.a; y := io.b }   io.z := x   io.v := y === 0.U   }

I can't find a how to write a build.sbt and class instantiation for converting it in Verilog.

回答1:

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.11.12"  resolvers ++= Seq(   Resolver.sonatypeRepo("snapshots"),   Resolver.sonatypeRepo("releases") )  libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.0.+"

Put the above GCD source code in GCD.scala and add the following to the file:

object GCDDriver extends App {   chisel3.Driver.execute(args, () => new GCD) }

You can then generate the Verilog by running: sbt "runMain GCDDriver". The default output directory is the current directory>

You can see what command-line options are available by running sbt "runMain GCDDriver --help" For example --target-dir will let you change the target directory

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