cortex-m3 | 易学教程

Using newlib's malloc in an ARM Cortex-M3

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问题 I'm creating code for an ARM Cortex-M3 (NXP's LCP17xx). I've been using static memory up to now and everything worked well. I tried to add dynamic memory support, but once I call malloc, the system gets stuck. I'm compiling with gcc for arm bare metal, and using newlib. Version: gcc-arm-none-eabi-4_6-2012q1 To add malloc support, I implemented a simple _sbrk function and modified my linker script to make some space for the heap (I've read many different tutorials about this part, but none

灵动微内核Cortex-M3八大知识点

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近两年随着电子产品智能需求提升，灵动微通用类MCU需求暴涨，例如仅仅一个智能门就需要三颗MCU如果需要实现无线控制，还需要能支持无线蓝牙的的MCU。而对于低阶机器人来说，就需要23颗MCU ，高阶机器人需要30多颗MCU，此外如果需要机器人有表情，则需要更多MCU，还有如果机器人融入更多情绪功能则需要的MCU还会更多。而Cortex-M3内核MCU是目前使用比较广泛的。MCU目前使用内核常用的有Cortex-M3，Cortex-M0/MO+，Cortex-M4.下面介绍比较常用Cortex-M3的八个知识点 Cortex-M3的八个知识点 1.指令集 32位ARM指令集：对应ARM状态 16位Thumb指令集：对应Thumb状态（是ARM指令集的一个子集）指令集演进图 2.BKP备份寄存器（42个16位寄存器组成），用来存储用户应用程序数据。在Vdd掉电时由Vbat供电。。在待机复位、系统复位、电源复位后，这些寄存器不会被复位 3.不再像别的ARM7那样从thumb状态和ARM状态来回切换 Thumb-2指令集横空出世，Cortex-M3不支持ARM指令集 4.DMA用来提供外设和存储器以及存储器和存储器之间的高速数据传输，而不需要CPU干预。当DMA和CM3核同时访问相同的目标（外设或者RAM）时，总线仲裁器会循环调度，确保CM3核得到至少一半的系统总线带宽。 5

On core_cm4.h why is there casting like ((uint32_t)(int32_t)IRQn)?

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问题 In the following code from core_cm4.h why is there a double cast ((uint32_t)(int32_t)IRQn) ? For example in the following function: __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } What is the purpose of this? 回答1: Since CM4 software implements negative interrupt sources for core, you have to cast value first to 32bit signed integer and later to unsigned 32bit to make proper right

arm gcc toolchain as arm-elf or arm-none-eabi, what is the difference?

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问题 When you build a gcc toolchain there is the possibility to build it as arm-elf or as arm-none-eabi, but what is the difference? I use the eabi today, but that is just since everyone else seem to do that... but since that is a really bad argument, it would be really nice to understand the difference. Note: This toolchain will crosscompile code for Cortex-M3 based mcu:s like the stm32. Thanks Some links : EABI: http://en.wikipedia.org/wiki/Application_binary_interface http://infocenter.arm.com

Disable IRQ on STM32

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问题 Is there any way to disable all irq from Cortex M3 MCU except one ? My issue is that I have a system running several kinds of irq with various priority levels and I want to disable all irq except one in a particular state. I know I can disable all irq by using "__disable_irq()" instruction but I can't enable one irq after calling this instruction if I didn't call "__enable_irq()" before. Thanks for your help, Regards 回答1: Use the BASEPRI register to disable all interrupts below the specified

How to set ARM user app start address when using USB bootloader?

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问题 Just picked up one of these ARM Cortex-M3 LPC1768 mini boards from eBay. It's basically a breakout board. However, based on what little documentation came with it, I've determined that it has a USB bootloader similar to that described by NXP's LPC1700 secondary USB bootloader (AN10866) app note. Both docs (the app note and board docs) indicate that user programs are to be built such that their starting address is 0x2000 . Because the USB bootloader is already at 0x0 and takes up 8K . Both

IAP on LPC 1768

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问题 I am trying to use IAP (in application programming) to copy the code of a function from one point in memory space to another (I know this doesn't have any use, but this is absolutely crucial for a project that I'm working on). The copying of the code seems to work with out a hitch, but when I call the copied function it always results in hardfaults. The function I'm copying doesn't have any references to other functions or data (It is a simple return function), so there is no problem of

Segmentation fault caused/avoided by changing source file order in Makefile

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问题 I'm developing software on an embedded platform and keep getting inexplicable (to me) segmentation faults. I was hoping to get some debugging ideas from those of you with more embedded platform experience. I couldn't find any useful information with a google search. Details: C++ compiled with GCC-ARM toolchain (4.9.3) ARM Cortex-M3 processor (on a LPC1768 dev board, if you're curious) I can prevent the segmentation fault by modifying the build order of the source files (i.e., file order in

How to determine if a word(4 bytes) is a 16-bit instruction or 32-bit instruction?

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问题 How do I know if the bytes in the word represent a 16-bit instruction or a 32-bit instruction ? I referred the ARM ARMv7M and I am not clear how to distinguish if it a 16-bit instruction or a 32-bit instruction. It says If bits [15:11] of the halfword being decoded take any of the following values, the halfword is the first halfword of a 32-bit instruction: • 0b11101 • 0b11110 • 0b11111. Otherwise, the halfword is a 16-bit instruction Does it mean that the processor always fetches halfwords,

arm cortex m3 display

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问题 hi i am working on arm controller lm3s8962 i m not able to understand the code below as per my understanding it is checking if the character is from the array or not, which he created using the ascii characters{i.e in the while loop : while(*pcStr != 0) }, i am not able to get what he is doing in the code after the line "Build and display the character buffer" plz can anyone explain this void RIT128x96x4StringDraw(const char *pcStr, unsigned long ulX, unsigned long ulY, unsigned char ucLevel)