xilinx

NI Labview FPGA: ERROR:Portability:3 - Xilinx Application has run out of memory

由 守給你的承諾、 提交于 2021-02-11 09:54:14
问题 I am using NI Labview FPGA to compile and synthesise a design onto the FPGA and have encountered the following error: LabVIEW FPGA: The compilation failed due to a Xilinx error. Details: ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 4025524 kb. You can try increasing your system's physical or virtual memory. If you are using a Win32 system, you can increase your application memory from 2GB to 3GB using the /3G

Yocto u-boot Custom Commands

由 ＊爱你＆永不变心＊ 提交于 2021-02-10 19:56:52
问题 What is the correct way of adding custom commands to u-boot in a Yocto setup (currently using Petalinux 2016.4 by Xilinx)? Should I add the relevant source files to the u-boot source through a recipe/patch, to be included in the compilation of u-boot? Is there a better way to do this during development to get a faster turn around. In what folder should the code be placed - under u-boot/board or added to u-boot/commands? Thanks 回答1: IMHO you have two options for adding the additional

Is there a way to pass a design parameter from a custom IP to software

由 我是研究僧i 提交于 2021-02-10 05:43:48
问题 I have a custom IP with some design parameters. They are exposed from the IP so I can customize them when using the IP in a block design. I want to be able to use those parameters inside my firmware code. For example when using a simple GPIO there are several parameters exposed in the xparameters.h header: #define XPAR_GPIO_0_BASEADDR 0x41200000 #define XPAR_GPIO_0_HIGHADDR 0x4120FFFF #define XPAR_GPIO_0_DEVICE_ID XPAR_GPIO_DEVICE_ID #define XPAR_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_GPIO_0

Xilinx AXI-IIC Slave Protocol description

由 白昼怎懂夜的黑 提交于 2021-01-27 18:10:14
问题 I am trying to get the Xilinx AXI IIC-Core example to work, which can be found at C:\Xilinx\14.7\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\iic_v2_08_a\examples\xiic_slave_example.c . Has anyone experiences with this core? I found this pg090 axi iic description, which says that Standard communication on the bus between a master and a slave is composed of four parts: - START - Slave Address - Data Transfer - STOP But when I transmit an write transfer, both address and message where accepted

Utilities Zynq in a PL only configuration

由 帅比萌擦擦* 提交于 2021-01-14 02:47:52
Is it possible to utilize Zynq in a PL-only configuration? You don’t need to have the ARM instantiated in your design but nevertheless the ARM is always present to take care of the configuration task. The Boot ROM code will always get executed at POR and the hard PS will boot. Remember, Zynq is a standalone processor and does not require PL configuration as is needed for MicroBlaze. Here is what you need to do if you are using PL only: Create an FSBL for the board (FSBL is needed for loading the bitstream). If you already have an SDK project for this board for any reference design (just make

How can I make each module instance read from a unique file?

由 江枫思渺然 提交于 2020-12-26 11:16:30
问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

How can I make each module instance read from a unique file?

由 感情迁移 提交于 2020-12-26 11:13:05
问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

How can I make each module instance read from a unique file?

由 一笑奈何 提交于 2020-12-26 11:08:00
问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

Vitis IDE invalid arguments

由 别等时光非礼了梦想. 提交于 2020-07-10 10:29:06
问题 I'm trying to create a boot image with TCL script on xsct console. But getting error. I couldn't find where I made a mistake. I couldn't find any results in Xilinx's documents and other forums. ERROR: source /home/nmi/Desktop/load.tcl Invalid arguments, name or processor not specified setws /home/nmi/workspace platform active zc702 app create -name fsbl -hw /home/nmi/Desktop/projeHDF/base_zynq_wrapper.xsa proc ps7_cortexa9_0 -os standalone -template {Zynq FSBL} app build -name fsbl exec

VHDL: Button debouncing (or not, as the case may be)

由 [亡魂溺海] 提交于 2020-06-28 05:14:32
问题 I've read through the other posts but can't seem to fix mine. I'm new to VHDL so I'm sure it's a simple fix. In short, the button isn't debouncing. The code compiles and the bitstream programs. In the testbench, button presses work, but the output LEDs don't change. On the board, pressing a button makes random LEDs light up (I presume because of bouncing). According to the schematic the inputs are going through the debouncers. Can anyone identify the issue? And any other hints and tips are
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