rdrand

This is a follow up to What is "=qm" in extended assembler . When using RDRAND , it sets (or unsets) the Carry Flag ( CF ): char rc; unsigned int val; __asm__ volatile( "rdrand %0 ; setc %1" : "=r" (val), "=qm" (rc) ); // 1 = success, 0 = underflow if(rc) { // use val ... } Are the FLAGS and EFLAGS registers considered part of condition control so that it conveys the proper information to the compiler? Should the above be written as: __asm__ volatile( "rdrand %0 ; setc %1" : "=r" (val), "=qm" (rc) : : "cc" ); Or is the use of "cc" spurious? I know its harmless to use if unneeded. From Extended

I was looking at H.J. Lu's PATCH: Update x86 rdrand intrinsics . I can't tell if I should be using _rdrand_u64 , _rdrand64_step , or if there are other function(s). There does not appear to be test cases written for them. There also seems to be a lack of man pages (from Ubuntu 14, GCC 4.8.4): $ man -k rdrand rdrand: nothing appropriate. How does one use the RDRAND intrinsics to generate, say, a block of 32 bytes? A related question is RDRAND and RDSEED intrinsics GCC and Intel C++ . But it does not tell me how to use them, or how to generate a block. If you look at <immintrin.h> (mine is in `

After reviewing the Intel Digital Random Number Generator (DRNG) Software Implementation Guide , I have a few questions about what happens to the internal state of the generator when RDRAND is invoked. Unfortunately the answers don't seem to be in the guide. According to the guide, inside the DRNG there are four 128-bit buffers that serve random bits for RDRAND to drain. RDRAND itself will provide either 16, 32, or 64 bits of random data depending on the width of the destination register: rdrand ax ; put 16 random bits in ax rdrand eax ; put 32 random bits in eax rdrand rax ; put 64 random

Does Intel C++ compiler and/or GCC support the following intrinsics, like MSVC does since 2012 / 2013? int _rdrand16_step(uint16_t*); int _rdrand32_step(uint32_t*); int _rdrand64_step(uint64_t*); int _rdseed16_step(uint16_t*); int _rdseed32_step(uint32_t*); int _rdseed64_step(uint64_t*); And if these intrinsics are supported, since which version are they supported (with compile-time-constant please)? Both GCC and Intel compiler support them. GCC support was introduced at the end of 2010. They require the header <immintrin.h> . GCC support has been present since at least version 4.6, but there

I have seen that Intel seems to have included a new assembly function to get real random numbers obtained from hardware. The name of the instruction is RdRand , but only a small amount of details seem accessible on it on Internet: http://en.wikipedia.org/wiki/RdRand My questions concerning this new instruction and its use in C++11 are the following: Are the random numbers generated with RdRand really random? (each bit generated from uncorrelated white noise or quantum processes? ) Is it a special feature of Ivy Bridge processors and will Intel continue to implement this function in the next

I cannot find any info on agner.org on the latency or throughput of the RDRAND instruction. However, this processor exists, so the information must be out there. Edit: Actually the newest optimization manual mentions this instruction. It is documented as <200 cycles, and a total bandwidth of at least 500MB/s on Ivy Bridge. But some more in-depth statistics on this instruction would be great since the latency and throughput is variable. I wrote librdrand. It's a very basic set of routines to use the RdRand instruction to fill buffers with random numbers. The performance data we showed at IDF is