powerpc

问题 I cross-compiled NET-SNMP 5.7.1 from sources to a PowerPC using ELDK-3.1. When I try to load the snmpd daemon in my embedded board, I see the message: # snmpd -f -Lo pcilib: Cannot open /proc/bus/pci pcilib: Cannot find any working access method. Of course my PPC board has no PCI, and I wonder why is netsnmp looking for it. In more than one place I see this same message (sourceforge, mail-archive, google-groups), but ir has no answer at all. Another variant, with a little but unhelpful

问题 I have a custom board with freescale P1010 processor in which P1010's eTSEC2 ( Enhanced 3-speed Ethernet controller) port is directly connected to Marvell 88E6046 ethernet switch Port 9 in SGMII mode. Linux (3.17) DSA driver is able to probe and detect switch ( Port 9 is 'cpu' whereas port 0 and 1 are designated as 'lan1' and 'lan2'). The problem however is, that there is no PHY for switch to attach to ( 'ifconfig up' fails to attach to ethx). U-boot creates a 'generic PHY' eth0 since it

问题 I have a custom board with freescale P1010 processor in which P1010's eTSEC2 ( Enhanced 3-speed Ethernet controller) port is directly connected to Marvell 88E6046 ethernet switch Port 9 in SGMII mode. Linux (3.17) DSA driver is able to probe and detect switch ( Port 9 is 'cpu' whereas port 0 and 1 are designated as 'lan1' and 'lan2'). The problem however is, that there is no PHY for switch to attach to ( 'ifconfig up' fails to attach to ethx). U-boot creates a 'generic PHY' eth0 since it

问题 I use Node.js for several jobs on my web apps and so far everthing's ok. But the Node.js uses Google's V8 as the default Javascript engine (JSE) and V8 runs exlusively on the x86 and ARM Instruction Set Architectures (ISA). Now I have a PPC processor Mac computer on which I want to run the Node.js . To do that, I'm adviced to use the Rhino + OpenJDK Shark Virtual Machine + Low Level Virtual Machine (LLVM) as the JIT compiler. Currently, that looks like the most applicable way of running Node

问题 I'm trying to discover Clang's equivalent to GCC's __builtin_darn() on Power9. Grepping Clang 7.0 sources it looks like LLVM supports it: llvm_source$ cat llvm/test/MC/PowerPC/ppc64-encoding.s | grep darn -B 1 -A 1 # CHECK-BE: darn 2, 3 # encoding: [0x7c,0x43,0x05,0xe6] # CHECK-LE: darn 2, 3 # encoding: [0xe6,0x05,0x43,0x7c] darn 2, 3 However, I can't seen to find the builtin: llvm_source$ grep -IR darn | grep builtin llvm_source$ What is Clang equivalent of GCC's __builtin_darn() ? 回答1: You

问题 I am trying to setup a driver for an embedded PowerPC board, and the correct way to do this today is to use the OpenFirmware Device Tree datastructure (the .dtb file, compiled from a .dts file). Creating a tree is pretty easy, but how do I get my device driver to find its node and the data in it? I have not managed to find any good reference on this, and books like "Linux Device Drivers" are too much into x86 land to be of much help for device trees that mostly pertain to Power Architecture

问题 I am trying to setup a driver for an embedded PowerPC board, and the correct way to do this today is to use the OpenFirmware Device Tree datastructure (the .dtb file, compiled from a .dts file). Creating a tree is pretty easy, but how do I get my device driver to find its node and the data in it? I have not managed to find any good reference on this, and books like "Linux Device Drivers" are too much into x86 land to be of much help for device trees that mostly pertain to Power Architecture

问题 I'm working on a PowerPC machine with in-core crypto. I'm having trouble porting AES key expansion from big endian to little endian using built-ins. Big endian works, but little endian does not. The algorithm below is the snippet presented in an IBM blog article. I think I have the issue isolated to line 2 below: typedef __vector unsigned char uint8x16_p8; uint8x64_p8 r0 = {0}; r3 = vec_perm(r1, r1, r5); /* line 1 */ r6 = vec_sld(r0, r1, 12); /* line 2 */ r3 = vcipherlast(r3, r4); /* line 3 *

问题 I hope to find some help even if this issue might be more hardware than software related (we'll see). I'm working on a custom board based on Freescales P1021 processor (ppc, e500v2 core). A external PCB will be connected and could be configured by SPI. The specifications of this external PCB reads as it expects a 2-byte command in full duplex mode and that only the last byte is used to transfer data back on MISO. Knowing this i currently work to prepare some pieces of software to test this

问题 I am using ldd to show the dynamic library on Fedora/x86, and it shows different results each time it is used. Is that expected? Or is there an explanation? I remember it shows a fixed result on PPC/Linux. `ldd /bin/ls linux-gate.so.1 => (0x00e5b000) librt.so.1 => /lib/librt.so.1 (0x00c0c000) libselinux.so.1 => /lib/libselinux.so.1 (0x0095d000) libcap.so.2 => /lib/libcap.so.2 (0x00110000) libacl.so.1 => /lib/libacl.so.1 (0x00331000) libc.so.6 => /lib/libc.so.6 (0x00115000) libpthread.so.0 =>