pci | 易学教程

Address mapping of PCI-memory in Kernel space

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问题 I'm trying to read and write to and PCI-device from a loadable kernel module. Therefore I follow this post: pci_enable_device(dev); pci_request_regions(dev, "expdev"); bar1 = pci_iomap(dev, 1, 0); // void iowrite32(u32 val, void __iomem *addr) iowrite32( 0xaaaaaaaa, bar1 + 0x060000); /* offset from device spec */ But at the end the device doesn't do his work as expected. Then I look to the address behind bar1 and found a very big value ffffbaaaaa004500 . At this point I don't really

CentOS下查看电脑硬件设备属性命令

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如何在linux下查看电脑硬件设备属性 # uname -a # 查看内核/操作系统/CPU信息 # head -n 1 /etc/issue # 查看操作系统版本 # cat /proc/cpuinfo # 查看CPU信息 # hostname # 查看计算机名 # lspci -tv # 列出所有PCI设备 # lsusb -tv # 列出所有USB设备 # lsmod # 列出加载的内核模块 # env # 查看环境变量资源 # free -m # 查看内存使用量和交换区使用量 # df -h # 查看各分区使用情况 # du -sh # 查看指定目录的大小 # grep MemTotal /proc/meminfo # 查看内存总量 # grep MemFree /proc/meminfo # 查看空闲内存量 # uptime # 查看系统运行时间、用户数、负载 # cat /proc/loadavg # 查看系统负载磁盘和分区 # mount | column -t # 查看挂接的分区状态 # fdisk -l # 查看所有分区 # swapon -s # 查看所有交换分区 # hdparm -i /dev/hda # 查看磁盘参数(仅适用于IDE设备) # dmesg | grep IDE # 查看启动时IDE设备检测状况网络 # ifconfig #

Linux allocates memory at specific physical address

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问题 I am testing a PCI Endpoint driver, I would like to do simple copy from the PCI RootPort side to the PCI Endpoint side. In PCI Endpoint side, we have address translation from PCI address to CPU physical address. We can configure the CPU physical address in the translation so that it maps to the specific DRAM region. The problem is how can we allocate a memory buffer at that specific CPU physical address to make sure the write from RootPort side really works? Any recommendations are

pci_alloc_consistent uncached memory

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问题 Is it fair to say that pci_alloc_consistent allocates a contiguous non-cached, non-paged kernel memory chunk. The reason I'm asking is that I saw this comment in some kernel/driver code (not in vanilla kernel sources), and I think I understand that the memory is presented as contiguous, however not sure that it's allocated non-cached, because the idea of cache coherency is to maintain data in the cache and DMA memory consistent. Also, not sure why they call it non-paged. E.g. https://www

Detailed PCI-E information, Windows

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问题 I have a project going where i need to gather information from a computer with graphic cards, from 1 up to 12, it has. This information is then saved in the cloud to be used later on. What i need, to a minimun is: What GPU it is How much memory Which PCI-slot it is using, 1, 2, 3 etc (or whatever name it is) Windows WMI seems to have some information, and i have been looking through the different classes but it seems difficult to find the PCI-E slot. Do anyone know how to get this information

How do cdev and its associated file operation work?

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Actually working on a PCI driver. I have two PCIe cards with same device ID and vendor ID. So to make a difference, I assign these two cards with two different MINOR numbers. //request for device numbers error = alloc_chrdev_region(&devt, 0, cards_found, DEVICE_NAME); if (error == 0) { major = MAJOR(devt); printk(KERN_INFO "(drv_init): MAJOR number is %d\n", major); printk(KERN_INFO "(drv_init): MINOR number range from 0 to %d\n", cards_found-1); cdevs = cdev_alloc(); cdevs->owner = THIS_MODULE; cdev_init(cdevs, fops); for(i=0;i<cards_found,i++) { devt = MKDEV(major, i); error = cdev_add(cdevs

Retrieving PCI coordinates by Windows' API (user mode)

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问题 Is there a way to obtain PCI coordinates (bus/slot/function numbers) of devices by using Windows c/c++ API (e.g PnP Configuration Manager API)? I already know how to do it in kernel mode, I need an user-mode solution. My target system is Windows XP-32 bit. 回答1: I've eventually found a simple solution (it was just a matter of digging into MSDN). This minimal code finds the device's PCI coordinates in terms of bus/slot/function: DWORD bus, addr, slot, func; HDEVINFO h; // Obtained by

PCIe事务层包TLP Header详解

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1、事务层包的一般格式：包的header为3DW（double word）或者4DW（一个DW代表4字节），数据负载为1~1024DW（即4~4096byte，最大4M），TLP Digest可选，TLP Digest表示检查，即CRC校验可选，长度为1DW（4byte）， TLP header的格式和内容会随着TLP的类型和路由（ID、Address、implcit）方式而改变，TLP的类型由Fmt（Format）决定，类型由type决定，关于byte enable，分为Last DW Byte Enables和First DW Byte Enables，在PCIe中Data Payload的单位是DW，也就是说数据大小（地址）需要以双字进行对齐，优势数据的大小并不是DW的整数倍，因此引入了Byte Enable来解决该问题，需要遵循的原则为：（1）、Byte enable为高电平有效，低电平表示Data Payload对应的byte为无效，不被completer使用。（2）、如果有效数据小于1DW，即小于4byte，则last DW byte enable应全部为0. （3）、如果有效数据大于1DW，则Last DW byte enable 中至少有一位有效（4）、如果有效数据大于等于3DW，则first DW byteenable和关于TLP的Data

Determine what (if any) PCI devices are plugged into motherboard PCI(e) slots

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I am writing a program in C# to perform a hardware audit across many Windows XP workstations. I need to determine which PCI devices are actual cards connected via a motherboard slot - NOT onboard devices that also use the PCI buses (built into the motherboard). I can successfully list all devices that use all the PCI buses using a variety of WMI classes, but none provide any indication of what is onboard vs. what is connected via a slot. I am not fussy about how the information is retrieved or from where it sourced (e.g. Pinvoke, WMI, registry, etc) as long as it's reliable. Thank you! After

PCIe事务层の详解（一）

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PCIe总线的通信机制：当一个设备要想另一个设备进行读取通信时，请求方requester需要向另一个设备发送请求request，靶向方作为事件完成方completer，以complete Packet的形式返回数据或者错误信息。请求的形式有：内存（memory）、输入输出（IO），配置（Configuration）和消息（Message） non-posted和posted的区别是是否仅仅将数据发送到接收方就完成动作，non_posted是指请求方发送了一个包含请求的Packet之后，还要得到一个包含completion的Packet的应答，posted指的是发出请求后，不需要completer发送一个包进行应答。显然，posted类型的操作对总线的利用效率更高。事务层包（Transaction Layer Packet，TLP）的几种类型： abbreviated :缩写 TLP的传输层示意图：图中的示意图以发送和接收为例，用户层将数据发送到事务层，事务层给数据加上帧头，并在数据的结尾添加ECRC(端到端CRC校验)信息，再发送给数据链路层（Data Link Layer）,护具链路层给接收到的TLP添加网络封包序号和数据链路层CRC校验结果，之后将数据发送到物理层，物理层给接收到的报添加其实和结束标志。接收方反向操作。事务层包的结构图为：图中的TLP

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