How to declare input and output types in verilog
问题 I have this top module that instantiate two modules: fillRam fillRam1( .clk(mclk), .ramaddrb(ramaddrb), .romaddrb(romaddrb), .romoutb(romoutbwire), .raminb(raminb)); vga vgainst( .ck(mclk), .HS(HS), .VS(VS), .outRed(OutRed), .outGreen(OutGreen), .outBlue(OutBlue), .sw(sw), .romouta(romoutawire), .ramouta(ramoutawire), .romaddra(romaddra), .ramaddra(ramaddra)); In this top module, i also have two module that makes the connections on the RAM and ROM. rom rom_instance ( .clka(mclk), // input