python myhdl package how to generate verilog initial block
问题 From the code mostly from the sample of myhdl: from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog __debug = True def ClkDriver(clk): halfPeriod = delay(10) @always(halfPeriod) def driveClk(): clk.next = not clk return driveClk def HelloWorld(clk, outs): counts = intbv(3)[32:] @always(clk.posedge) def sayHello(): outs.next = not outs if counts >= 3 - 1: counts.next = 0 else: counts.next = counts + 1 if __debug__: print "%s Hello World! outs %s %s" % ( now(), str(outs),