count leading zero in single cycle datapath
问题 As you all might know that the MIPS instruction set supports clz (count leading zero) as follows: clz $t0,$t1 count leading zeros t0 = # of leading zeros in t1 I am writing a single cycle datapath in verilog and was just wondering what the ALU needs to support in order for me to do this... any ideas?? 回答1: Here's a possible approach (I'm ignoring the case of an input of 0, which is probably best treated as a special case): The number of leading zeros in a 32-bit number is either: the number