mesi | 易学教程

x86 MESI invalidate cache line latency issue

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问题 I have the following processes , I try to make ProcessB very low latency so I use tight loop all the time and isolate cpu core 2 . global var in shared memory : int bDOIT ; typedef struct XYZ_ { int field1 ; int field2 ; ..... int field20; } XYZ; XYZ glbXYZ ; static void escape(void* p) { asm volatile("" : : "g"(p) : "memory"); } ProcessA (in core 1 ) while(1){ nonblocking_recv(fd,&iret); if( errno == EAGAIN) continue ; if( iret == 1 ) bDOIT = 1 ; else bDOIT = 0 ; } // while ProcessB ( in

MESI protocol. Write with cache miss. Why needs main memory value fetch?

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问题 I'm wondering about MESI protocol implementation of writing with the allocation on write miss policy . Let's say that we have write request and got cache miss with no other copies of cache line. This diagram says that the next step is to fetch value from main memory (or L2 cache), store it and mark cache line as M (modified). I suppose then the new value is stored in cache block. The question is: Why we need the step of fetching data from main memory? Why we can't simply write the new value

MESI protocol. Write with cache miss. Why needs main memory value fetch?

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What cache coherence solution do modern x86 CPUs use?

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问题 I am somewhat confused with what how cache coherence systems function in modern multi core CPU. I have seen that snooping based protocols like MESIF/MOESI snooping based protocols have been used in Intel and AMD processors, on the other hand directory based protocols seem to be a lot more efficient with multiple core as they don't broadcast but send messages to specific nodes. What is the modern cache coherence solution in AMD or Intel processors, is it snooping based protocols like MOESI and

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

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问题 In C#, this is the standard code for invoking an event in a thread-safe way: var handler = SomethingHappened; if(handler != null) handler(this, e); Where, potentially on another thread, the compiler-generated add method uses Delegate.Combine to create a new multicast delegate instance, which it then sets on the compiler-generated field (using interlocked compare-exchange). (Note: for the purposes of this question, we don't care about code that runs in the event subscribers. Assume that it's

CAS指令与MESI缓存一致性协议

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【推荐】2019 Java 开发者跳槽指南.pdf(吐血整理) >>> 转： CAS（Compare-And-Swap）指令是并行程序设计最基础的基石，随着越来越多的本本都用上了双核，这个世界已经快速步入并行计算时代，CAS指令发挥的作用也就越来越大。CAS指令，在Intel CPU上称为CMPXCHG，的作用是将指定内存地址的内容与所给的某个值相比，如果相等，则将其内容替换为所给的另一个值，这一系列操作是原子的，不可能被中断。基本上所有的同步机制，与信号量、Java中的synchronized等的实现最终都要用到CAS指令，即使锁无关的数据结构也离不开CAS指令。关于CAS指令最著名的传闻是CAS需要锁总线，因此CAS指令不但慢而且会严重影响系统并发度，即使没有冲突是也一样。不过在较新的CPU中（对于Intel CPU来说是486之后），事实并非如此。目前的CPU一般都采用了很好的缓存一致性协议，在很多情况下能够防止锁总线的发生，这其中最著名的就是Intel CPU中使用的MESI缓存一致性协议。先来说说缓存一致性问题。为了提高数据访问效率，每个CPU上都有一个容量很小（现在一般是1M这个数量级），速度很快的缓存，用于缓存最常访问的那些数据。由于操作内存的速度实在太慢，数据被修改时也只更新缓存，并不直接写出到内存中去，这一来就造成了缓存中的数据与内存不一致

When CPU flush value in storebuffer to L1 Cache?

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问题 Core A writes value x to storebuffer, waiting invalid ack and then flushes x to cache. Does it wait only one ack or wait all acks ? And how does it konw how many acks in all CPUs ? 回答1: It isn't clear to me what you mean by "invalid ack", but let's assume you mean a snoop/invalidation originating from another core which is requesting ownership of the same line. In this case, the stores in the store buffer are generally free to ignore such invalidations from other cores since the stores in the

What is the point of MESI on Intel 64 and IA-32

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问题 The point of MESI is to retain a notion of a shared memory system. However, with store buffers, things are complicated: Memory is coherent downstream of once the data hits the MESI-implementing caches. However, upstream of that, each core may disagree on what is in memory location X, dependent on what is in each core's local store buffer. As such, it seems like, from the viewpoint of each core, that the state of memory is different - it is not coherent. So, why do we bother "partially"

MESI cache protocol

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问题 I was reading about the MESI snooping cache coherence protocol, which I guess is the protocol that is used in modern multicore x86 processors (please correct me if I'm wrong). Now that article says this at one place. A cache that holds a line in the Modified state must snoop (intercept) all attempted reads (from all of the other caches in the system) of the corresponding main memory location and insert the data that it holds. This is typically done by forcing the read to back off (i.e. retry