memory-model

When reading about consistency models (namely the x86 TSO), authors in general resort to models where there are a bunch of CPUs, their associated store buffers and their private caches. If my understanding is correct, store buffers can be described as queues where CPUs may put any store instruction they want to commit to memory. So as the name states, they are store buffers. But when I read those papers, they tend to talk about the interaction of loads and stores, with statements such as "a later load can pass an earlier store" which is slightly confusing, as they almost seem to be talking as

I am reading C++ Concurrency in Action by Anthony Williams. Currently I at point where he desribes memory_order_consume. After that block there is: Now that I’ve covered the basics of the memory orderings, it’s time to look at the more complex parts It scares me a little bit, because I don't fully understand several things: How dependency-ordered-before differs from synchronizes-with? They both create happens-before relationship. What is exact difference? I am confused about following example: int global_data[]={ … }; std::atomic<int> index; void f() { int i=index.load(std::memory_order

In the C++ memory model, there is a total order on all loads and stores of all sequentially consistent operations. I'm wondering how this interacts with operations that have other memory orderings that are sequenced before/after sequentially consistent loads. For example, consider two threads: std::atomic<int> a(0); std::atomic<int> b(0); std::atomic<int> c(0); ////////////// // Thread T1 ////////////// // Signal that we've started running. a.store(1, std::memory_order_relaxed); // If T2's store to b occurs before our load below in the total // order on sequentially consistent operations, set

The Intel 64 and IA-32 Architectures Software Developer's Manual says the following about re-ordering of actions by a single processor (Section 8.2.2, "Memory Ordering in P6 and More Recent Processor Families"): Reads may be reordered with older writes to different locations but not with older writes to the same location. Then below when discussing points where this is relaxed compared to earlier processors, it says: Store-buffer forwarding, when a read passes a write to the same memory location. As far as I can tell, "store-buffer forwarding" isn't precisely defined anywhere (and neither is

I'm watching this video by Herb Sutter on GPGPU and the new C++ AMP library. He is talking about memory models and mentions Weak Memory Models and then Strong Memory Models and I think he's referring to read/write ordering etc, but I am however not sure. Google turns up some interesting results (mostly science papers) on memory models, but can someone explain what is a Weak Memory Model and what is a Strong Memory Model and their relation to concurrency? In terms of concurrency, a memory model specifies the constraints on data accesses, and the conditions under which data written by one thread

Assume you've got the following definitions: struct X { char a, b; }; X x; And now assume you have two threads, one of which reads and writes x.a but never accesses x.b while the other one reads and writes x.b but never accesses x.a . Neither thread uses any locks or other synchronization primitives. Is this guaranteed to work in C++11? Or does it count as accessing the same object, and therefore need a lock? It's safe. Quoting C++11: [intro.memory]p3: A memory location is either an object of scalar type or a maximal sequence of adjacent bit-fields all having non-zero width. [ Note: Various