memory-model

问题 I am studying this site: https://gcc.gnu.org/wiki/Atomic/GCCMM/AtomicSync, which is very helpful to understand the topic about atomic class. But this example about relaxed mode is hard to understand: /*Thread 1:*/ y.store (20, memory_order_relaxed) x.store (10, memory_order_relaxed) /*Thread 2*/ if (x.load (memory_order_relaxed) == 10) { assert (y.load(memory_order_relaxed) == 20) /* assert A */ y.store (10, memory_order_relaxed) } /*Thread 3*/ if (y.load (memory_order_relaxed) == 10) assert

问题 Say, I create an object of type Foo in thread #1 and want to be able to access it in thread #3. I can try something like: std::atomic<int> sync{10}; Foo *fp; // thread 1: modifies sync: 10 -> 11 fp = new Foo; sync.store(11, std::memory_order_release); // thread 2a: modifies sync: 11 -> 12 while (sync.load(std::memory_order_relaxed) != 11); sync.store(12, std::memory_order_relaxed); // thread 3 while (sync.load(std::memory_order_acquire) != 12); fp->do_something(); The store/release in thread

问题 I have written a simple 'envelope' class to make sure I understand the C++11 atomic semantics correctly. I have a header and a payload, where the writer clears the header, fills in the payload, then fills the header with an increasing integer. The idea is that a reader then can read the header, memcpy out the payload, read the header again, and if the header is the same the reader can then assume they successfully copied the payload. It's OK that the reader may miss some updates, but it's not

问题 I'm trying to compile and link a simple program to a DOS .com file using Turbo C compiler and linker. By that I try the simplest C-program I can think of. void main() {} Are there command line arguments to link to com files in the Turbo C Linker? The Error Message I get from the Linker is the following: "Fatal: Cannot generate COM file: invalid entry point address" I know that com files need entry point to be at 100h. Does Turbo C have an option to set this address? 回答1: It has been a long

问题 I'm trying to compile and link a simple program to a DOS .com file using Turbo C compiler and linker. By that I try the simplest C-program I can think of. void main() {} Are there command line arguments to link to com files in the Turbo C Linker? The Error Message I get from the Linker is the following: "Fatal: Cannot generate COM file: invalid entry point address" I know that com files need entry point to be at 100h. Does Turbo C have an option to set this address? 回答1: It has been a long

问题 This question is a follow-up/clarification to this: Does the MOV x86 instruction implement a C++11 memory_order_release atomic store? This states the MOV assembly instruction is sufficient to perform acquire-release semantics on x86. We do not need LOCK , fences or xchg etc. However, I am struggling to understand how this works. Intel doc Vol 3A Chapter 8 states: https://software.intel.com/sites/default/files/managed/7c/f1/253668-sdm-vol-3a.pdf In a single-processor (core) system.... Reads

问题 This question is a follow-up/clarification to this: Does the MOV x86 instruction implement a C++11 memory_order_release atomic store? This states the MOV assembly instruction is sufficient to perform acquire-release semantics on x86. We do not need LOCK , fences or xchg etc. However, I am struggling to understand how this works. Intel doc Vol 3A Chapter 8 states: https://software.intel.com/sites/default/files/managed/7c/f1/253668-sdm-vol-3a.pdf In a single-processor (core) system.... Reads

问题 we all know the idea of stack and heap, but I recently read about a third option to save data: registers. I have a hard time finding good articles about this type, what I found was: http://www.dotnetperls.com/method-parameter, and a lot of stuff for C, for example: http://igoro.com/archive/volatile-keyword-in-c-memory-model-explained/ The only real informations I have so far: every CPU has its own registers, which can be used to save data, which is accessed at the fastest way possible, for

问题 The paper N4455 No Sane Compiler Would Optimize Atomics talks about various optimizations compilers can apply to atomics. Under the section Optimization Around Atomics, for the seqlock example, it mentions a transformation implemented in LLVM, where a fetch_add(0, std::memory_order_release) is turned into a mfence followed by a plain load, rather than the usual lock add or xadd . The idea is that this avoids taking exclusive access of the cacheline, and is relatively cheaper. The mfence is

问题 The paper N4455 No Sane Compiler Would Optimize Atomics talks about various optimizations compilers can apply to atomics. Under the section Optimization Around Atomics, for the seqlock example, it mentions a transformation implemented in LLVM, where a fetch_add(0, std::memory_order_release) is turned into a mfence followed by a plain load, rather than the usual lock add or xadd . The idea is that this avoids taking exclusive access of the cacheline, and is relatively cheaper. The mfence is