makefile

问题 I'm trying to write a Makefile for a project. With that, I was able to build the project whenever there is a change in any of the C files. But, it doesn't build when there is a change in a header file. So, I'm trying Makefile for a simpler directory structure and if it works I'm planning to do the same in the main project. The directory structure is, src -> code1 -> file1.c src -> code2 -> file2.c src -> code1inc -> file1.h src -> code2inc -> file2.h All the files together should build and

问题 I have a project with CMakeLists.txt and 7 executables with it: /Project /build /Subprogram1 /Subprogram2 ... /Subprogram7 CMakeLists.txt My CMakeLists.txt : project(Project) cmake_minimum_required(VERSION 2.8) set( CMAKE_CXX_FLAGS "-O0 -Wall -pedantic -std=c++11" ) include_directories( "${PROJECT_SOURCE_DIR}/headers" ) include_directories( "${PROJECT_SOURCE_DIR}/Subprogram1/headers" ) include_directories( "${PROJECT_SOURCE_DIR}/Subprogram2/headers" ) include_directories( "${PROJECT_SOURCE

问题 This is a part of my makefile : SRC = ./ DIRS = src libs/maths libs/struct BIN_DIR = ./bin/ SRC_DIRS= $(foreach dir, $(DIRS), $(addprefix $(SRC), $(dir))) SRC_TEST= $(sort $(SRC_DIRS)) SRCS = $(foreach msrc, $(SRC_DIRS), $(wildcard $(msrc)/*.c)) DEL_PRE = $(foreach target, $(SRCS), $(notdir $(target))) ADD_PRE = $(foreach target, $(DEL_PRE), $(addprefix $(BIN_DIR), $(target))) OBJS = $(ADD_PRE:.c=.o) .PHONY: all clean re all: $(EXEC) $(EXEC): $(OBJS) $(CC) $(OBJS) -o $@ $(LDLIBS) $(OBJS): $

问题 i'm not sure why my makefiles isn't working. i googled the the error and i got some stuff about whitespaces and tabs but i'm not sure what to do. error: makefile:17: * missing separator. Stop. # see http://www.gnu.org/software/make/manual/make.html # http://www.gnu.org/software/make/manual/make.html#Automatic-Variables CXX=g++ CXXFLAGS=-c -Wall -g LDFLAGS= OBJECTS= main.o Player.o Territory.o Continent.o Game.o Color.o TITLE=ass1 ARCHIVE=$(TITLE).tar.gz .PHONY : all clean debug valgrind

问题 $(EXEX) : main% : $(OBJS) pp%.o gcc $(FLAGS) $^ -o $@ I am just trying to understand the above. As I understand it, everything in EXEX are targets which will be built using the following pattern. main, OBJS and pp.o are prerequisites for things in EXEX. The second line will compile $^(meaning all the prereqs) using gcc with all the flags in FLAGS as object files in order to build $@ which is the contents of EXEX. There need to be rules to build all those -o's. My question is why are there two

问题 I'm trying to have a makefile variable for the content of a directory after that directory has been updated by a recipe. Why does this not work : A_FILE = $(wildcard subdir/*) all: a @echo $(A_FILE) a: @mkdir ./subdir @touch subdir/b @touch a $ rm -rf ./subdir && make $ ...whereas this does: A_FILE = $(wildcard subdir/*) all: a @echo $(A_FILE) a: subdir/b @touch a subdir/b: @mkdir ./subdir @touch subdir/b $ rm -rf ./subdir && make subdir/b $ ? I thought lazy-evaluation meant the variable was

问题 I am trying to install Rundeck from source. I have tried three different distributions of Linux (a Debian, Red Hat, and SUSE distribution). All have had failures. I install the make command, Java and Git before proceeding. The "make" command is what fails on every distribution of Linux that I have tried. The "./gradlew build" command was no more successful either. I then run these commands: cd /tmp git clone https://github.com/rundeck/rundeck.git mv rundeck /opt/ cd /opt/rundeck make I always

问题 This question already has answers here : Why does the library linker flag sometimes have to go at the end using GCC? (2 answers) Closed 6 years ago . Command like this will work: (LD) $(LDFLAGS) -o reip.app newlib/crt0.o reip.o renetif.o fs.o httpd.o liblwip.a newlib/libc.a But if I place *.a before *.o files - it will be not able to find functions from libs. I've searched through some old projects and found in makefiles lines like these: $(CC) $(LIBS) -o $(TARGET) JukeboxMain.o JukeboxPlayer

问题 Below is the folder structure for my code. This is a very small example to understand the concept of multiple makefiles based on which I have to create makefile for bigger code structure. work ├── code | | | └── main.h and test.h files here │ └── main.c and test.c files here | └── subdir.mk | ├── _Build/ │ └── Makefile here I am keeping both Makefile and subdir.mk files to be very basic and simple to grasp the concept. Below is the code for subdir.mk #subdir.mk #==============================

问题 I'm trying to cross-compile the LiME Kernel Module for the android-goldfish-3.10-n-dev ( commit: 3a3b199582a68ba0688a099147738d6c99f3282d ) Linux Kernel version with the following Makefile: obj-m := lime.o lime-objs := tcp.o disk.o main.o KDIR_GOLD := /path/to/goldfish PWD := $(shell pwd) CCPATH :=/path/to/x86_64-linux-android-4.9/bin default: # cross-compile for Android emulator $(MAKE) ARCH=x86_64 CROSS_COMPILE=$(CCPATH)/x86_64-linux-android- -C $(KDIR_GOLD) M="$(PWD)" modules $(CCPATH)/x86