interrupt

Why does my SWI instruction hang? (BeagleBone Black, ARM Cortex-A8 cpu)

由 十年热恋 提交于 2019-12-09 04:53:27
I'm starting to write a toy OS for the BeagleBone Black , which uses an ARM Cortex-A8-based TI Sitara AM3359 SoC and the U-Boot bootloader. I've got a simple standalone hello world app writing to UART0 that I can load through U-Boot so far, and now I'm trying to move on to interrupt handlers, but I can't get SWI to do anything but hang the device. According to the AM335x TRM (starting on page 4099, if you're interested), the interrupt vector table is mapped in ROM at 0x20000. The ROM SWI handler branches to RAM at 0x4030ce08, which branches to the address stored at 0x4030ce28. (Initially, this

Jumping from one firmware to another in MCU internal FLASH

由 落花浮王杯 提交于 2019-12-09 00:13:24
问题 I am currently working on a bootloader firmware application targeted to STM32F030C8. I specified in my scatter file that the bootloader app will occupy main memory location 0x08000000 to 0x08002FFF (sector 0 to sector 2). I also wrote a main firmware application that is stored from 0x08003000 to 0x0800C800. After downloading both firmware to the MCU internal FLASH, I lauched the main app from the bootloader using the code below: /************************************************************//*

What happens in the x86 architecture when an interrupt occurs?

由 ＊爱你＆永不变心＊ 提交于 2019-12-08 23:51:52
问题 I'm studying x86 and Real Time Systems, and I have a question, that is: Which steps x86 follows to handle any interrupt ? 回答1: When an interrupt occurs, the CPU does the following: Push the current address (contents of the Instruction Pointer) onto the stack; also, push the processor flags (but not all the other processor registers) Jump to the address of the ISR (Interrupt Service Routine), which is specified in the Interrupt Descriptor Table. The ISR should do the following: Push any

BIOS Interrupts in protected mode

由 ＊爱你＆永不变心＊ 提交于 2019-12-08 17:20:47
问题 I'm working on an operating system project, using isolinux (syslinux 4.5) as bootloader, loading my kernel with multiboot header organised at 0x200000. As I know the kernel is already in 32-bit protected mode. My question: Is there any easier way to get access to BIOS Interrupts? (Basically I want 0x10 :D) After loading, my kernel sets up its own GDT and IDT entries and further remaps IRQs. So, is it possible to jump into real mode just after the kernel is loaded and set up VGA/SVGA modes

Is it a good way to close a thread?

由 独自空忆成欢 提交于 2019-12-08 14:10:45
问题 I have a short version of the question: I start a thread like that: counter.start(); , where counter is a thread. At the point when I want to stop the thread I do that: counter.interrupt() In my thread I periodically do this check: Thread.interrupted() . If it gives true I return from the thread and, as a consequence, it stops. And here are some details, if needed: If you need more details, they are here. From the invent dispatch thread I start a counter thread in this way: public static void

java: console application main thread spawns a key listener thread

由 …衆ロ難τιáo~ 提交于 2019-12-08 13:09:24
问题 I wrote a tool, which is performing some steps 1..n Some of the steps require user interaction (reading from System.in) Other steps loop until some condition is fulfilled or the user pressed some key (When the user pressed the key the loop should end and the main should go to the next step) What I did for those steps, that provide a key loop interruption is to spawn a thread which reads from System.in -> this thread then interrupts the step, if key was pressed. This works fine, but when the

Different ways to to trigger a SMI for a processor

由 吃可爱长大的小学妹 提交于 2019-12-08 11:56:30
问题 I am writing some firmware code running in the System Managemnt Mode (SMM) on an Intel platform. I want to fully understand how my SMI handler get started. I read from the Intel Manual that: The only way to enter SMM is by signaling an SMI through the SMI# pin on the processor or through an SMI message received through the APIC bus. And I also read that a synchronous SMI can be triggered by writing to an I/O port . My understanding is like this: SMM is just a special operating mode of a

Level Triggered Interrupt handling and nested interrupts

由 六眼飞鱼酱① 提交于 2019-12-08 08:47:33
问题 [Updated question as GIC v2 has 3 registers ACK, EOIR, DIR] This is the most basic question which I need someone else to clarify and state that the sequence below is correct. In the following arch, [Core] ----- [ Interrupt Controller ] --Level Triggered -- [Device] a. Device Raises the Level and informs the Interrupt Controller b. Interrupt controller triggers core of an interrupt. (Assuming core's interrupts enabled) c. Assuming the Interrupt controller is GIC (used with ARM) and it has 3

Ruby, windows, active_record, and Control-C

由 孤人 提交于 2019-12-08 08:17:24
问题 What is active_record doing to the signal processes under windows (I don't see this with the same versions on the mac) that causes it to behave so strangely? For instance: require 'rubygems' trap("INT"){puts "interrupted"} puts __LINE__ sleep 5 require 'active_record' trap("INT"){puts "interrupted again"} puts __LINE__ sleep 5 When I run the above code (ruby 1.8.6, gem 1.3.1, activerecord 2.2.2,) I can hit ^C as many times as I like during the first sleep, but the first interrupt after the

interrupt one thread inside another thread's run method in Java

由 人走茶凉 提交于 2019-12-08 08:14:33
问题 I was reading this post and the suggestions given to interrupt one thread from another is " " " Here are a couple of approaches that should work, if implemented correctly. You could have both threads regularly check some common flag variable (e.g. call it stopNow), and arrange that both threads set it when they finish. (The flag variable needs to be volatile ... or properly synchronized.) You could have both threads regularly call the Thread.isInterrupted() method to see if it has been
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