interrupt-handling

问题 I studied interrupts vs cyclical polling and learnt the advantages of interrupts that don't have to wait for a poll. Polling seemed to me just like event-driven programming or at least similar to a listener and what the polling does is actually much like listening to input or output. Do you agree or did I misunderstand any crucial difference between polling (cyclical listening) and event-driven programming (also listening with so-called listeners)? 回答1: Nope, quite the contrary interrupt

问题 I studied interrupts vs cyclical polling and learnt the advantages of interrupts that don't have to wait for a poll. Polling seemed to me just like event-driven programming or at least similar to a listener and what the polling does is actually much like listening to input or output. Do you agree or did I misunderstand any crucial difference between polling (cyclical listening) and event-driven programming (also listening with so-called listeners)? 回答1: Nope, quite the contrary interrupt

问题 Is it possible to run multiple instances of a same interrupt simultaneously on a multi processor system in linux? If not possible, why do we need to synchronize between interrupt handlers using spin locks? Thanks Venkatesh 回答1: On a SMP architecture Advanced Programmable Interrupt Controller( APIC ) is used to route the interrupts from peripherals to the CPU's. the APIC, based on 1. the routing table (where interrupt affinity is set to a particular processor), 2. priority of the interrupt, 3.

问题 I'm doing some development in C with a STM32F107 chip and, at some point, the device began to reset when I call a specific function. I don't have a debugger and my debugging is just plain text over a serial port. I've used some other microcontrollers in which I was able to access a register to see the cause of the reset, but I can't seem to find an equivalent for this device. I'm aware of the hardware exceptions of the Cortex-M3, but I don't know if one of them is being triggered since I can

问题 I'm doing some development in C with a STM32F107 chip and, at some point, the device began to reset when I call a specific function. I don't have a debugger and my debugging is just plain text over a serial port. I've used some other microcontrollers in which I was able to access a register to see the cause of the reset, but I can't seem to find an equivalent for this device. I'm aware of the hardware exceptions of the Cortex-M3, but I don't know if one of them is being triggered since I can

问题 I am getting segmentation fault in the program below. This is for set the cursor on the top-left of the screen. But why i am getting segmentation fault on this program? Thanks for the replies. section .text global main main: mov ah, 2 mov bh, 1 mov dh, 0 mov dl, 0 int 10h I think that the problem is the protected mode that i am working. This is an 16-bit instruction and i am trying this in a 32-bit machine! Am i correct? I am running this program in a Linux Ubuntu distribution 32-bits. THe

问题 How do you properly set, and then reset, the keyboard ISR in DOS? (x86 assembly, real mode, 16 bit, with TASM) I have the following assembly code which sets up my ISR for the keyboard. All it is supposed to do is print out a sentence each time a key is pressed, up to five times. Then it is supposed to exit. It seems like the ISR is being installed correctly. It will print out a sentence each time a key is pressed (once for down, once for up). However, it appears as though I am uninstalling

问题 I am making embedded firmware where everything after initialization happens in ISRs. I have variables that are shared between them, and I am wondering in which cases they need to be volatile. I never block, waiting for a change in another ISR. When can I be certain that actual memory is read or written to when not using volatile? Once every ISR? Addendum: This is for ARM Cortex-M0, but this isn't really a question about ISRs as much as it is about compiler optimization, and as such, the

问题 I write some function in my OS kernel to issue the performance monitoring interrupt (PMI) on instructions counter overflow. It works well on my machine (Intel core i5). But when I run it on qemu using qemu-system-x86_64 -enable-kvm -cpu host -m 256 -serial mon:stdio -cdrom var/run/hypervisor.iso the interrupt does never fire. Is there anything I am missing? Does it require any special configuration to get the PMI fired on qemu? I recall that instruction counting works well in qemu. msr

问题 I write some function in my OS kernel to issue the performance monitoring interrupt (PMI) on instructions counter overflow. It works well on my machine (Intel core i5). But when I run it on qemu using qemu-system-x86_64 -enable-kvm -cpu host -m 256 -serial mon:stdio -cdrom var/run/hypervisor.iso the interrupt does never fire. Is there anything I am missing? Does it require any special configuration to get the PMI fired on qemu? I recall that instruction counting works well in qemu. msr