intel

问题 Commonly, cacheline is 64B but atomicity of non-volatile memory is 8B. For example: x[1]=100; x[2]=100; clflush(x); x is cacheline aligned, and is initially set to 0 . System crashs in clflush(); Is it possible x[1]=0 , x[2]=100 after reboot？ 回答1: Under the following assumptions: I assume that the code you've shown represents a sequence of x86 assembly instructions rather than actual C code that is yet to be compiled. I also assume that the code is being executed on a Cascade Lake processor

问题 I notice that Intel Tremont has 64 bytes store instructions with MOVDIRI and MOVDIR64B. Those guarantees atomic write to memory, whereas don't guarantee the load atomicity. Moreover, the write is weakly ordered, immediately followed fencing may be needed. I find no MOVDIRx in IceLake. Why doesn't Ice Lake need such instructions like MOVDIRx ? (At the bottom of page 15) Intel® ArchitectureInstruction Set Extensions and Future FeaturesProgramming Reference https://software.intel.com/sites

问题 I'm seeing 15% performance degradation of the same C++ code compiled to exactly same machine instructions but located on differently aligned addresses. When my tiny main loop starts at 0x415220 it's faster then when it is at 0x415250. I'm running this on Intel Core2 Duo. I use gcc 4.4.5 on x86_64 Ubuntu. Can anybody explain the cause of slowdown and how I can force gcc to optimally align the loop? Here is the disassembly for both cases with profiler annotation: 415220 576 12.56%

问题 X86 guarantees a total order over all stores due to its TSO memory model. My question is if anyone has an idea how this is actually implemented. I have a good impression how all the 4 fences are implemented, so I can explain how local order is preserved. But the 4 fences will just give PO; it won't give you TSO (I know TSO allows older stores to jump in front of newer loads so only 3 out of 4 fences are needed). Total order over all memory actions over a single address is responsibility of

问题 I want to look into how latest processors differs from standard RISC V implementation (RISC V having 5 stage pipeline - fetch, decode, memory , ALU , Write back) but not able to find how should I start approaching the problem so as to find the current implementation of pipelining at processor I tried referring Intel documentation for i7-4510U documentation but it was not much help 回答1: Haswell's pipeline length is reportedly 14 stages (on a uop-cache hit), 19 stages when fetching from L1i for

问题 The L1/L2 cache are inclusive in Intel and L1 / L2 cache is 8 way associativity, means in a set there are 8 different cache lines exist. The cache lines are operated as a whole, means if I want to remove few bytes from a cache line, the whole cache line will be removed , not the only those bytes which I want to remove. Am I right ? Now, my question is whenever a cache line of a set is removed/evicted from cache, either by some other process or by using clflush(manual eviction of a cache line

问题 I'm a student doing some research on Hyper-threading recently. I'm a little confused about the feature - L1 Data Cache Context Mode. In the architecture optimization manual, it was described that L1 cache can operate in two modes: The first level cache can operate in two modes depending on a context-ID bit: Shared mode: The L1 data cache is fully shared by two logical processors. Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical

问题 I'm a student doing some research on Hyper-threading recently. I'm a little confused about the feature - L1 Data Cache Context Mode. In the architecture optimization manual, it was described that L1 cache can operate in two modes: The first level cache can operate in two modes depending on a context-ID bit: Shared mode: The L1 data cache is fully shared by two logical processors. Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical

来源： https://stackoverflow.com/questions/64255426/simple-instruction-encode

来源： https://stackoverflow.com/questions/64754316/writeback-of-clean-cache-lines-in-skylake