instruction-set

问题 How is it that an executable can work on both AMD and Intel systems. Aren't AMD's and Intel's instruction sets different? How does the executable work on both? How exactly do they compile the files to work like that. And what exactly is the role of the OS in all this? 回答1: Essentially these days, compilation is done for the OS not for hardware, as most hardware have universal protocols and/or tech, as mentioned above, x86 or x64 machine code/opcodes/instruction sets, some programmers do make

问题 How is it that an executable can work on both AMD and Intel systems. Aren't AMD's and Intel's instruction sets different? How does the executable work on both? How exactly do they compile the files to work like that. And what exactly is the role of the OS in all this? 回答1: Essentially these days, compilation is done for the OS not for hardware, as most hardware have universal protocols and/or tech, as mentioned above, x86 or x64 machine code/opcodes/instruction sets, some programmers do make

问题 The orpd instruction is a "bitwise logical OR of packed double precision floating point values". Doesn't this do exactly the same thing as por ("bitwise logical OR")? If so, what's the point of having it? 回答1: Remember that SSE1 orps came first. (Well actually MMX por mm, mm/mem came even before SSE1.) Having the same opcode with a new prefix be the SSE2 orpd instruction makes sense for hardware decoder logic, I guess, just like movapd vs. movaps . Several instructions like this are redundant

问题 The orpd instruction is a "bitwise logical OR of packed double precision floating point values". Doesn't this do exactly the same thing as por ("bitwise logical OR")? If so, what's the point of having it? 回答1: Remember that SSE1 orps came first. (Well actually MMX por mm, mm/mem came even before SSE1.) Having the same opcode with a new prefix be the SSE2 orpd instruction makes sense for hardware decoder logic, I guess, just like movapd vs. movaps . Several instructions like this are redundant

问题 First I am a little bit confused with the differences between movq and movabsq , my text book says: The regular movq instruction can only have immediate source operands that can be represented as 32-bit two’s-complement numbers. This value is then sign extended to produce the 64-bit value for the destination. The movabsq instruction can have an arbitrary 64-bit immediate value as its source operand and can only have a register as a destination. I have two questions to this. Question 1 The

问题 First I am a little bit confused with the differences between movq and movabsq , my text book says: The regular movq instruction can only have immediate source operands that can be represented as 32-bit two’s-complement numbers. This value is then sign extended to produce the 64-bit value for the destination. The movabsq instruction can have an arbitrary 64-bit immediate value as its source operand and can only have a register as a destination. I have two questions to this. Question 1 The

问题 I want to know how do lis and ori instructions work? There is a description IBM description which i cannot understand well. Could someone explain to me what is the result on this example: lis r1, 0x0028 ori r1, r1, 0x776F 回答1: lis is defined here ( http://www-01.ibm.com/support/knowledgecenter/api/content/nl/en-us/ssw_aix_53/com.ibm.aix.aixassem/doc/alangref/fixed_point_load.htm#idx175 ) Extended Mnemonic lis rx, value => Equivalent to addis rx, 0, value . aka Load Immediate Shifted addis is

问题 I am not able to understand the difference between Instruction set and Instruction set architecture. I know what is an instruction set . Instruction set just defines the possible instructions we can give to the processor and how the instruction are give ( therefore the instruction format ) to the processor. Now what is Instruction set architecture ? I have looked up wikipedia, it has a page on instruction set and inside it, on the first line there is a link to instruction set architecture

问题 I am not able to understand the difference between Instruction set and Instruction set architecture. I know what is an instruction set . Instruction set just defines the possible instructions we can give to the processor and how the instruction are give ( therefore the instruction format ) to the processor. Now what is Instruction set architecture ? I have looked up wikipedia, it has a page on instruction set and inside it, on the first line there is a link to instruction set architecture

问题 I am reading a book "Computer Organization and Design RISC-V Edition" , and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded immediate field. S-B types separate the immediate field into 2 parts. This makes sense since all instructions encoding has to be similar. But I cannot understand why the immediate field is encoded in this way below. imm[12, 10:5], imm[4:1, 11] instead of imm[11:5], imm[4:0] U-J types also have this