gpgpu

Let's take the nVidia Fermi Compute Architecture . It says: The first Fermi based GPU, implemented with 3.0 billion transistors, features up to 512 CUDA cores. A CUDA core executes a floating point or integer instruction per clock for a thread. The 512 CUDA cores are organized in 16 SMs of 32 cores each. [...] Each CUDA processor has a fully pipelined integer arithmetic logic unit (ALU) and floating point unit (FPU). [...] In Fermi, the newly designed integer ALU supports full 32-bit precision for all instructions, consistent with standard programming language requirements. The integer ALU is

I had the idea about a warp based parallel reduction since all threads of a warp are in sync by definition. So the idea was that the input data can be reduced by factor 64 (each thread reduces two elements) without any synchronization need. Same as the original implementation by Mark Harris the reduction is applied on block-level and data is on shared memory. http://gpgpu.org/static/sc2007/SC07_CUDA_5_Optimization_Harris.pdf I created a kernel to test his version and my warp based version. The kernel itself is completely identically storing BLOCK_SIZE elements in shared memory and outputting

I know that devices before the Fermi architecture had 8 SPs in a single multiprocessor. Is the count same in Fermi architecture? The number of Multiprocessors (MP) and the number of cores per MP can be found by executing DeviceQuery.exe . It is found in the %NVSDKCOMPUTE_ROOT%/C/bin directory of the GPU Computing SDK installation. A look at the code of DeviceQuery (found in %NVSDKCOMPUTE_ROOT%/C/src/DeviceQuery ) reveals that it the number of cores is calculated by passing the x.y CUDA Capability numbers to the ConvertSMVer2Cores utility function. From the code of ConvertSMVer2Cores this

We are considering porting an application from a dedicated digital signal processing chip to run on generic x86 hardware. The application does a lot of Fourier transforms, and from brief research, it appears that FFTs are fairly well suited to computation on a GPU rather than a CPU. For example, this page has some benchmarks with a Core 2 Quad and a GF 8800 GTX that show a 10-fold decrease in calculation time when using the GPU: http://www.cv.nrao.edu/~pdemores/gpu/ However, in our product, size constraints restrict us to small form factors such as PC104 or Mini-ITX, and thus to rather limited

If you have work items executing in a wavefront and there is a conditional such as: if(x){ ... } else{ .... } What do the work-items execute? is it the case whereby all workitems in the wavefront will execute the first branch (i.e. x == true ). If there are no work-items for which x is false, then the rest of the conditional is skipped? What happens if one work-item takes the alternative path. Am I told that all workitems will execute the alternate path as well (therefore executing both paths?). Why is this the case and how does it not mess up the program execution talonmies NVIDIA gpus use