fsm

问题 I have seen the following used to make state changes in Verilog modules: state <= 2'b10; state <= #1 IDLE; Why is <= used and not just =? What is the purpose of using #1? Does it make a difference? Here is some Verilog code for a FSM that shows the first one being used. Would it work the same if it was replaced with the second? module fsm( clk, rst, inp, outp); input clk, rst, inp; output outp; reg [1:0] state; reg outp; always @( posedge clk, posedge rst ) begin if( rst ) state <= 2'b00;

问题 I have a state machine with 6 states(3 main states). Only the last state is working but the first 2 doesn't(out of 3).Only the last state is working. I found out the problem, when I remove the debounce circuit it works, but I need the debouncing circuit. I got the debouncing circuit from the internet. I would be glad if someone can help. type SM_STATES is (state_column_1, scan_col_1, state_column_2, scan_col_2, state_column_3, scan_col_3); signal my_state : SM_STATES := state_column_1; Below

问题 Just wondering if I'm implementing a finite state machine in VHDL whether or not I need to state what all of the outputs are in every possible state? Even if I know that some outputs won't change from one state to the other and I know that the order of the states will also be in the same order? For example, in this (forced) example: entity test is port ( clk : in std_logic; a : in std_logic; b: out std_logic; c: out std_logic; ); end test; architecture Behavioral of test is type

问题 I'm having problems understanding a game scene manager (FSM) in pygame that I try to replicate from this website: https://nicolasivanhoe.wordpress.com/2014/03/10/game-scene-manager-in-python-pygame/ I'll copy the code: # -*- encoding: utf-8 -*- # Modules import pygame, sys class Director: """Represents the main object of the game. The Director object keeps the game on, and takes care of updating it, drawing it and propagate events. This object must be used with Scene objects that are defined

问题 So I've recently started learning VHDL as part of a practicum at the university. This time, our task was to create a moore-machine on which you can set the time in a certain way and use it as a countdown, triggering an alarm as soon as it reaches 0. The starting state is "idle", if you press "keySet_in" you can set the minutes by pressing "keyUp_in" to increase it or "keyDown_in" to decrease it. If you press any other key, the countdown will go to "start" and start with the default value of 1

问题 I have been trying to design an RS-232 receiver taking an FSM approach. I will admit that I do not have a very well-rounded understanding of VHDL, so I have been working on the code on the fly and learning as I go. However, I believe I've hit a brick wall at this point. My issue is that I have two processes in my code, one to trigger the next state and the other to perform the combinational logic. My code is as follows: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ASyncReceiverV4 is Port

问题 i am trying out this pretty neat tool called Yosys to synthesize my Verilog designs. i want to export out the FSM in my Verilog design using the Yosys command fsm_export but it does not generate anything. I wonder how is this command supposed to be called? the series of commands i called were: read_verilog qwerty.v ; fsm_export if the generation is successful and i have the FSM in KISS2 format, anyone knows what (open source) tools are there to allow me to visualize the FSM? thanks a bunch!

问题 I would like to create a bunch of "and" and "or" and "not" gates in a directed graph. And then traverse from the inputs to see what they results are. I assume there is a ready made traversal that would do that but I don't see it. I don't know what the name of such a traversal would be. Certainly breadth first will not do the job. I need to get ALL the leaves, and go up toward the root. In other words A = (B & (C & Z)) I need to resolve C @ Z first. I need to put this type of thing in a graph

问题 I have an Akka FSM actor that runs the following pseudocode after receiving a message while in ReadyState lookupA ! Wrapper(Lookup("A")) lookupB ! Wrapper(Lookup("B")) lookupC ! Wrapper(Lookup("C")) goto(LookingUpDataState) using DataFound(a = None, b = None, c = None) The actor then waits for responses which can be either FullResult[T] (extending ServiceResult[T] ) or Empty (extending ServiceResult[Nothing] ). Successful lookup results are used to populate the DataFound instance's fields and

问题 I am reading a file that is filled with hex numbers. I have to identify a particular pattern, say "aaad" (without quotes) from it. Every time I see the pattern, I generate some data to some other file. This would be a very common case in designing programs - parsing and looking for a particular pattern . I have designed it as a Finite State Machine and structured structured it in C using switch-case to change states. This was the first implementation that occured to me. DESIGN: Are there some