cpu

How are the modern Intel CPU L3 caches organized?

你说的曾经没有我的故事 提交于 2019-12-10 11:47:25
问题 Given that CPUs are now multi-core and have their own L1/L2 caches, I was curious as to how the L3 cache is organized given that its shared by multiple cores. I would imagine that if we had, say, 4 cores, then the L3 cache would contain 4 pages worth of data, each page corresponding to the region of memory that a particular core is referencing. Assuming I'm somewhat correct, is that as far as it goes? It could, for example, divide each of these pages into sub-pages. This way when multiple

CPU expensive javascript

浪子不回头ぞ 提交于 2019-12-10 10:58:38
问题 I plan to replicate the statistics javascript from BBC News, but I'm intrigued by the CPU usage of that script (after you press the Start button). Can be an adding script so expensive? Can you tell me why that script is so CPU expensive? I'm new to javascript but i think that simple arithmetic operations are consuming too much client CPU. Is that ok? 回答1: The sheer amount of numbers being increased are the source of the high CPU usage. On my AMD Phenom II X2, it runs up about 19% of CPU on

C get cpu usage on linux and windows

不打扰是莪最后的温柔 提交于 2019-12-10 10:56:16
问题 I am using below programs on linux and windows to get cpu utilization of current processes. Linux: int main() { int ret; char *buf; int i=0; int who= RUSAGE_SELF; struct rusage usage; struct rusage *p=&usage; ret=getrusage(who,p); printf("user time used: %16lf %16lf\n",p->ru_utime.tv_sec,p->ru_utime.tv_usec); printf("system time used: %16lf %16lf\n",p->ru_stime.tv_sec,p->ru_stime.tv_usec); system("ls"); printf("user time used: %16lf %16lf\n",p->ru_utime.tv_sec,p->ru_utime.tv_usec); printf(

Checking CPU Popcount from C#

旧时模样 提交于 2019-12-10 10:50:19
问题 Does anyone know how to check the cpu in C# if it supports popcount(population count)? C++ is easy but trying to do some C++ to C# conversion with some chess code. Thanks much. 回答1: I have yet to find an easy way to detect and use special CPU instructions in C#. There are several options, none of them nice; asmjit a function that does popcount x86/x64 CPUID in C# mono has a simd library with datatype support (not popcount I guess) Use a C++ DLL (probably way slower because of overhead) .. I

How is the size of TLB in Intel's Sandy Bridge CPU determined?

北城余情 提交于 2019-12-10 10:44:20
问题 The wiki webpage(https://en.wikipedia.org/wiki/Sandy_Bridge) mentioned that Data TLB has 64, 32 and 4 entries respectively for 4KB, 2MB and 1GB pages. I found these numbers hard to understand. Sandy Bridge has a virtual address of 48 bits, which means for 4K page, there can be 2^36 pages, and for 2MB and 1GB pages, there should be 2^27 and 2^18 pages. If TLB has 64 entries for 4K page, the size of each entry should be no less than 6+36 = 42 bits. Why are there only 32 entries for 2M page,

Why each logical CPU has it's own CR3 register in case of multithreading?

人盡茶涼 提交于 2019-12-10 10:36:28
问题 When we have a CPU that supports some form of multithreading, each logical CPU has it's own set of registers (as a minimum), including a CR3 register. Since we are working on the vitual address space of the same process when executing different threads and a context switch never happens (neither the TLB cache gets invalidated when switching threads of the same process), why do we need a CR3 register to point to the page table and page directory in the logical CPU? Isn't the value always the

Would buffering cache changes prevent Meltdown?

微笑、不失礼 提交于 2019-12-10 07:44:37
问题 If new CPUs had a cache buffer which was only committed to the actual CPU cache if the instructions are ever committed would attacks similar to Meltdown still be possible? The proposal is to make speculative execution be able to load from memory, but not write to the CPU caches until they are actually committed. 回答1: TL:DR: yes I think it would solve Spectre (and Meltdown) in their current form (using a flush+read cache-timing side channel to copy the secret data from a physical register),

Handling CPU exceptions in C++

你说的曾经没有我的故事 提交于 2019-12-10 04:17:14
问题 is there a cross-platform way to handle the CPU exceptions like segmentation faults, or division by zero? Lets say, I need to call some potentially unsafe functions (for example from a plug-in file), that can cause a segfault, or some other problems that I cannot test before I execute it. I know, that the C standard library has signal handling functions, but I don't know how to use them to handle the problem to avoid the program termination (I guess, I can't just jump to the location before

tomcat7 cpu 占用率过高调整

微笑、不失礼 提交于 2019-12-10 02:30:30
之前在在catalina.sh中简单设置JAVA_OPTS=-Xms1024m -Xmx2048m,没起作用,CPU还是超高,机器内存限制再大也设不了了,转而到启动脚本里设置了这一堆参数,没有一个个的排查,到底哪个参数起作用,但实际效果很明显。 启动脚本将JAVA_OPTS参数设置: vi /etc/rc.d/init.d/tomcat #!/bin/bash # chkconfig: 2345 10 90 # description: Starts and Stops the Tomcat daemon. export CATALINA_HOME=/usr/local/tomcat/apache-tomcat-7.0.53 export JAVA_HOME=/usr/java/jdk1.7.0_55 export JAVA_OPTS="-server \ -Dfile.encoding=UTF-8 \ -Dcatalina.logbase=/home/webapp/logs/tomcat7 \ -Dnet.sf.ehcache.skipUpdateCheck=true -XX:+DoEscapeAnalysis -XX:+UseConcMarkSweepGC -XX:+CMSClassUnloadingEnabled -XX:+UseParNewGC -XX:

Trying to disable Processor idle states (C states) on Windows PC

不打扰是莪最后的温柔 提交于 2019-12-09 17:05:01
问题 I need to prevent the processor from entering an idle state (non C0 C state). Admittedly I do not know much about processor C and P states so bear with me. We use a camera from a third party vendor which occasionally delivers corrupted frames. The vendor has determined that when the CPU enters an idle state it interferes with the transmission of the frame over the firewire. To confirm this I used the following code on a Windows 7 PC and indeed, disabling the idle states resolved the issue. /